mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-05 13:29:22 +00:00
b0abb4dc42
the overloaded vector types allowed floating-point or integer vector elements. Most of these operations actually depend on the element type, so bitcasting was not an option. If you include the vpadd intrinsics that I updated earlier, this gets rid of 20 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78646 91177308-0d34-0410-b5e6-96231b3b80d8
118 lines
5.0 KiB
LLVM
118 lines
5.0 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
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%struct.__builtin_neon_v8qi2 = type { <8 x i8>, <8 x i8> }
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%struct.__builtin_neon_v4hi2 = type { <4 x i16>, <4 x i16> }
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%struct.__builtin_neon_v2si2 = type { <2 x i32>, <2 x i32> }
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%struct.__builtin_neon_v2sf2 = type { <2 x float>, <2 x float> }
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%struct.__builtin_neon_v16qi2 = type { <16 x i8>, <16 x i8> }
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%struct.__builtin_neon_v8hi2 = type { <8 x i16>, <8 x i16> }
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%struct.__builtin_neon_v4si2 = type { <4 x i32>, <4 x i32> }
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%struct.__builtin_neon_v4sf2 = type { <4 x float>, <4 x float> }
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define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK: vtrni8:
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;CHECK: vtrn.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vtrn.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v8qi2 %tmp3, 1
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%tmp6 = add <8 x i8> %tmp4, %tmp5
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ret <8 x i8> %tmp6
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}
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define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK: vtrni16:
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;CHECK: vtrn.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vtrn.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v4hi2 %tmp3, 1
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%tmp6 = add <4 x i16> %tmp4, %tmp5
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ret <4 x i16> %tmp6
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}
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define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK: vtrni32:
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;CHECK: vtrn.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call %struct.__builtin_neon_v2si2 @llvm.arm.neon.vtrn.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v2si2 %tmp3, 1
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%tmp6 = add <2 x i32> %tmp4, %tmp5
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ret <2 x i32> %tmp6
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}
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define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK: vtrnf:
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;CHECK: vtrn.32
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = call %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vtrn.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v2sf2 %tmp3, 1
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%tmp6 = add <2 x float> %tmp4, %tmp5
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ret <2 x float> %tmp6
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}
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define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK: vtrnQi8:
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;CHECK: vtrn.8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vtrn.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v16qi2 %tmp3, 1
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%tmp6 = add <16 x i8> %tmp4, %tmp5
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ret <16 x i8> %tmp6
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}
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define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK: vtrnQi16:
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;CHECK: vtrn.16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vtrn.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v8hi2 %tmp3, 1
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%tmp6 = add <8 x i16> %tmp4, %tmp5
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ret <8 x i16> %tmp6
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}
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define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK: vtrnQi32:
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;CHECK: vtrn.32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call %struct.__builtin_neon_v4si2 @llvm.arm.neon.vtrn.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v4si2 %tmp3, 1
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%tmp6 = add <4 x i32> %tmp4, %tmp5
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ret <4 x i32> %tmp6
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}
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define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK: vtrnQf:
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;CHECK: vtrn.32
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = call %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vtrn.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
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%tmp4 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 0
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%tmp5 = extractvalue %struct.__builtin_neon_v4sf2 %tmp3, 1
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%tmp6 = add <4 x float> %tmp4, %tmp5
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ret <4 x float> %tmp6
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}
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declare %struct.__builtin_neon_v8qi2 @llvm.arm.neon.vtrn.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare %struct.__builtin_neon_v4hi2 @llvm.arm.neon.vtrn.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare %struct.__builtin_neon_v2si2 @llvm.arm.neon.vtrn.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare %struct.__builtin_neon_v2sf2 @llvm.arm.neon.vtrn.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare %struct.__builtin_neon_v16qi2 @llvm.arm.neon.vtrn.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare %struct.__builtin_neon_v8hi2 @llvm.arm.neon.vtrn.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare %struct.__builtin_neon_v4si2 @llvm.arm.neon.vtrn.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare %struct.__builtin_neon_v4sf2 @llvm.arm.neon.vtrn.v4f32(<4 x float>, <4 x float>) nounwind readnone
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