mirror of
https://github.com/c64scene-ar/llvm-6502.git
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6b7d99d473
This patch replaces the control flow handling with a new pass which structurize the graph before transforming it to machine instruction. This has a couple of different advantages and currently fixes 20 piglit tests without a single regression. It is now a general purpose transformation that could be not only be used for SI/R6xx, but also for other hardware implementations that use a form of structurized control flow. v2: further cleanup, fixes and documentation Patch by: Christian König Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170591 91177308-0d34-0410-b5e6-96231b3b80d8
209 lines
9.4 KiB
TableGen
209 lines
9.4 KiB
TableGen
//===------------ AMDILInstrInfo.td - AMDIL Target ------*-tablegen-*------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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// This file describes the AMDIL instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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// AMDIL Instruction Predicate Definitions
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// Predicate that is set to true if the hardware supports double precision
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// divide
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def HasHWDDiv : Predicate<"Subtarget.device()"
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"->getGeneration() > AMDGPUDeviceInfo::HD4XXX && "
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"Subtarget.device()->usesHardware(AMDGPUDeviceInfo::DoubleOps)">;
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// Predicate that is set to true if the hardware supports double, but not double
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// precision divide in hardware
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def HasSWDDiv : Predicate<"Subtarget.device()"
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"->getGeneration() == AMDGPUDeviceInfo::HD4XXX &&"
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"Subtarget.device()->usesHardware(AMDGPUDeviceInfo::DoubleOps)">;
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// Predicate that is set to true if the hardware support 24bit signed
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// math ops. Otherwise a software expansion to 32bit math ops is used instead.
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def HasHWSign24Bit : Predicate<"Subtarget.device()"
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"->getGeneration() > AMDGPUDeviceInfo::HD5XXX">;
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// Predicate that is set to true if 64bit operations are supported or not
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def HasHW64Bit : Predicate<"Subtarget.device()"
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"->usesHardware(AMDGPUDeviceInfo::LongOps)">;
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def HasSW64Bit : Predicate<"Subtarget.device()"
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"->usesSoftware(AMDGPUDeviceInfo::LongOps)">;
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// Predicate that is set to true if the timer register is supported
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def HasTmrRegister : Predicate<"Subtarget.device()"
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"->isSupported(AMDGPUDeviceInfo::TmrReg)">;
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// Predicate that is true if we are at least evergreen series
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def HasDeviceIDInst : Predicate<"Subtarget.device()"
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"->getGeneration() >= AMDGPUDeviceInfo::HD5XXX">;
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// Predicate that is true if we have region address space.
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def hasRegionAS : Predicate<"Subtarget.device()"
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"->usesHardware(AMDGPUDeviceInfo::RegionMem)">;
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// Predicate that is false if we don't have region address space.
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def noRegionAS : Predicate<"!Subtarget.device()"
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"->isSupported(AMDGPUDeviceInfo::RegionMem)">;
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// Predicate that is set to true if 64bit Mul is supported in the IL or not
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def HasHW64Mul : Predicate<"Subtarget.calVersion()"
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">= CAL_VERSION_SC_139"
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"&& Subtarget.device()"
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"->getGeneration() >="
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"AMDGPUDeviceInfo::HD5XXX">;
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def HasSW64Mul : Predicate<"Subtarget.calVersion()"
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"< CAL_VERSION_SC_139">;
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// Predicate that is set to true if 64bit Div/Mod is supported in the IL or not
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def HasHW64DivMod : Predicate<"Subtarget.device()"
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"->usesHardware(AMDGPUDeviceInfo::HW64BitDivMod)">;
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def HasSW64DivMod : Predicate<"Subtarget.device()"
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"->usesSoftware(AMDGPUDeviceInfo::HW64BitDivMod)">;
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// Predicate that is set to true if 64bit pointer are used.
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def Has64BitPtr : Predicate<"Subtarget.is64bit()">;
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def Has32BitPtr : Predicate<"!Subtarget.is64bit()">;
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//===--------------------------------------------------------------------===//
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// Custom Operands
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//===--------------------------------------------------------------------===//
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def brtarget : Operand<OtherVT>;
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//===--------------------------------------------------------------------===//
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// Custom Selection DAG Type Profiles
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//===--------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Generic Profile Types
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//===----------------------------------------------------------------------===//
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def SDTIL_GenBinaryOp : SDTypeProfile<1, 2, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
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]>;
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def SDTIL_GenTernaryOp : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<2, 3>
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]>;
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def SDTIL_GenVecBuild : SDTypeProfile<1, 1, [
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SDTCisEltOfVec<1, 0>
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]>;
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//===----------------------------------------------------------------------===//
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// Flow Control Profile Types
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//===----------------------------------------------------------------------===//
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// Branch instruction where second and third are basic blocks
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def SDTIL_BRCond : SDTypeProfile<0, 2, [
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SDTCisVT<0, OtherVT>
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]>;
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//===--------------------------------------------------------------------===//
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// Custom Selection DAG Nodes
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//===--------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Flow Control DAG Nodes
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//===----------------------------------------------------------------------===//
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def IL_brcond : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
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//===----------------------------------------------------------------------===//
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// Call/Return DAG Nodes
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//===----------------------------------------------------------------------===//
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def IL_retflag : SDNode<"AMDGPUISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue]>;
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//===--------------------------------------------------------------------===//
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// Instructions
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//===--------------------------------------------------------------------===//
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// Floating point math functions
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def IL_div_inf : SDNode<"AMDGPUISD::DIV_INF", SDTIL_GenBinaryOp>;
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def IL_mad : SDNode<"AMDGPUISD::MAD", SDTIL_GenTernaryOp>;
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//===----------------------------------------------------------------------===//
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// Integer functions
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//===----------------------------------------------------------------------===//
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def IL_umul : SDNode<"AMDGPUISD::UMUL" , SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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//===--------------------------------------------------------------------===//
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// Custom Pattern DAG Nodes
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//===--------------------------------------------------------------------===//
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def global_store : PatFrag<(ops node:$val, node:$ptr),
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(store node:$val, node:$ptr), [{
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return isGlobalStore(dyn_cast<StoreSDNode>(N));
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}]>;
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//===----------------------------------------------------------------------===//
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// Load pattern fragments
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//===----------------------------------------------------------------------===//
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// Global address space loads
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def global_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return isGlobalLoad(dyn_cast<LoadSDNode>(N));
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}]>;
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// Constant address space loads
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def constant_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
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}]>;
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//===----------------------------------------------------------------------===//
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// Complex addressing mode patterns
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//===----------------------------------------------------------------------===//
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def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>;
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def ADDRF : ComplexPattern<i32, 2, "SelectADDR", [frameindex], []>;
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def ADDR64 : ComplexPattern<i64, 2, "SelectADDR64", [], []>;
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def ADDR64F : ComplexPattern<i64, 2, "SelectADDR64", [frameindex], []>;
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//===----------------------------------------------------------------------===//
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// Instruction format classes
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//===----------------------------------------------------------------------===//
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class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
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: Instruction {
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let Namespace = "AMDGPU";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let Pattern = pattern;
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let AsmString = !strconcat(asmstr, "\n");
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let isPseudo = 1;
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let Itinerary = NullALU;
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bit hasIEEEFlag = 0;
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bit hasZeroOpFlag = 0;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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//===--------------------------------------------------------------------===//
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// Multiclass Instruction formats
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//===--------------------------------------------------------------------===//
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// Multiclass that handles branch instructions
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multiclass BranchConditional<SDNode Op> {
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def _i32 : ILFormat<(outs),
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(ins brtarget:$target, GPRI32:$src0),
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"; i32 Pseudo branch instruction",
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[(Op bb:$target, GPRI32:$src0)]>;
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def _f32 : ILFormat<(outs),
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(ins brtarget:$target, GPRF32:$src0),
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"; f32 Pseudo branch instruction",
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[(Op bb:$target, GPRF32:$src0)]>;
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}
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// Only scalar types should generate flow control
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multiclass BranchInstr<string name> {
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def _i32 : ILFormat<(outs), (ins GPRI32:$src),
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!strconcat(name, " $src"), []>;
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def _f32 : ILFormat<(outs), (ins GPRF32:$src),
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!strconcat(name, " $src"), []>;
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}
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// Only scalar types should generate flow control
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multiclass BranchInstr2<string name> {
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def _i32 : ILFormat<(outs), (ins GPRI32:$src0, GPRI32:$src1),
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!strconcat(name, " $src0, $src1"), []>;
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def _f32 : ILFormat<(outs), (ins GPRF32:$src0, GPRF32:$src1),
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!strconcat(name, " $src0, $src1"), []>;
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}
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//===--------------------------------------------------------------------===//
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// Intrinsics support
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//===--------------------------------------------------------------------===//
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include "AMDILIntrinsics.td"
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