mirror of
https://github.com/c64scene-ar/llvm-6502.git
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36ba909184
v1i32, v2i32, v8i32 and v16i32. Only add VGPR register classes for integer vector types, to avoid attempts copying from VGPR to SGPR registers, which is not possible. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174632 91177308-0d34-0410-b5e6-96231b3b80d8
489 lines
16 KiB
C++
489 lines
16 KiB
C++
//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Custom DAG lowering for SI
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//
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//===----------------------------------------------------------------------===//
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#include "SIISelLowering.h"
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#include "AMDIL.h"
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#include "AMDILIntrinsicInfo.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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using namespace llvm;
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SITargetLowering::SITargetLowering(TargetMachine &TM) :
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AMDGPUTargetLowering(TM),
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TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())) {
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addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
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addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
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addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
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addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
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addRegisterClass(MVT::i1, &AMDGPU::SCCRegRegClass);
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addRegisterClass(MVT::i1, &AMDGPU::VCCRegRegClass);
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addRegisterClass(MVT::v1i32, &AMDGPU::VReg_32RegClass);
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addRegisterClass(MVT::v2i32, &AMDGPU::VReg_64RegClass);
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addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass);
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addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
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addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
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computeRegisterProperties();
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setOperationAction(ISD::AND, MVT::i1, Custom);
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setOperationAction(ISD::ADD, MVT::i64, Legal);
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setOperationAction(ISD::ADD, MVT::i32, Legal);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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// We need to custom lower loads from the USER_SGPR address space, so we can
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// add the SGPRs as livein registers.
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setOperationAction(ISD::LOAD, MVT::i32, Custom);
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setOperationAction(ISD::LOAD, MVT::i64, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::SETCC);
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}
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MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
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MachineInstr * MI, MachineBasicBlock * BB) const {
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const TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
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MachineRegisterInfo & MRI = BB->getParent()->getRegInfo();
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MachineBasicBlock::iterator I = MI;
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switch (MI->getOpcode()) {
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default:
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return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
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case AMDGPU::BRANCH: return BB;
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case AMDGPU::CLAMP_SI:
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BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(1))
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// VSRC1-2 are unused, but we still need to fill all the
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// operand slots, so we just reuse the VSRC0 operand
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.addOperand(MI->getOperand(1))
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.addOperand(MI->getOperand(1))
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.addImm(0) // ABS
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.addImm(1) // CLAMP
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.addImm(0) // OMOD
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.addImm(0); // NEG
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MI->eraseFromParent();
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break;
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case AMDGPU::FABS_SI:
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BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(1))
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// VSRC1-2 are unused, but we still need to fill all the
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// operand slots, so we just reuse the VSRC0 operand
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.addOperand(MI->getOperand(1))
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.addOperand(MI->getOperand(1))
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.addImm(1) // ABS
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.addImm(0) // CLAMP
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.addImm(0) // OMOD
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.addImm(0); // NEG
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MI->eraseFromParent();
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break;
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case AMDGPU::FNEG_SI:
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BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(1))
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// VSRC1-2 are unused, but we still need to fill all the
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// operand slots, so we just reuse the VSRC0 operand
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.addOperand(MI->getOperand(1))
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.addOperand(MI->getOperand(1))
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.addImm(0) // ABS
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.addImm(0) // CLAMP
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.addImm(0) // OMOD
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.addImm(1); // NEG
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MI->eraseFromParent();
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break;
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case AMDGPU::SHADER_TYPE:
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BB->getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType =
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MI->getOperand(0).getImm();
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MI->eraseFromParent();
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break;
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case AMDGPU::SI_INTERP:
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LowerSI_INTERP(MI, *BB, I, MRI);
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break;
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case AMDGPU::SI_INTERP_CONST:
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LowerSI_INTERP_CONST(MI, *BB, I, MRI);
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break;
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case AMDGPU::SI_WQM:
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LowerSI_WQM(MI, *BB, I, MRI);
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break;
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case AMDGPU::SI_V_CNDLT:
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LowerSI_V_CNDLT(MI, *BB, I, MRI);
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break;
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}
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return BB;
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}
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void SITargetLowering::LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WQM_B64), AMDGPU::EXEC)
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.addReg(AMDGPU::EXEC);
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MI->eraseFromParent();
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}
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void SITargetLowering::LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
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unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
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MachineOperand dst = MI->getOperand(0);
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MachineOperand iReg = MI->getOperand(1);
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MachineOperand jReg = MI->getOperand(2);
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MachineOperand attr_chan = MI->getOperand(3);
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MachineOperand attr = MI->getOperand(4);
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MachineOperand params = MI->getOperand(5);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
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.addOperand(params);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp)
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.addOperand(iReg)
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.addOperand(attr_chan)
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.addOperand(attr)
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.addReg(M0);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32))
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.addOperand(dst)
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.addReg(tmp)
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.addOperand(jReg)
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.addOperand(attr_chan)
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.addOperand(attr)
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.addReg(M0);
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MI->eraseFromParent();
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}
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void SITargetLowering::LowerSI_INTERP_CONST(MachineInstr *MI,
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MachineBasicBlock &BB, MachineBasicBlock::iterator I,
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MachineRegisterInfo &MRI) const {
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MachineOperand dst = MI->getOperand(0);
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MachineOperand attr_chan = MI->getOperand(1);
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MachineOperand attr = MI->getOperand(2);
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MachineOperand params = MI->getOperand(3);
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unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
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.addOperand(params);
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_MOV_F32))
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.addOperand(dst)
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.addOperand(attr_chan)
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.addOperand(attr)
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.addReg(M0);
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MI->eraseFromParent();
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}
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void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
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unsigned VCC = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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BuildMI(BB, I, BB.findDebugLoc(I),
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TII->get(AMDGPU::V_CMP_GT_F32_e32),
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VCC)
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.addReg(AMDGPU::SREG_LIT_0)
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.addOperand(MI->getOperand(1));
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32_e32))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(3))
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.addOperand(MI->getOperand(2))
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.addReg(VCC);
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MI->eraseFromParent();
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}
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EVT SITargetLowering::getSetCCResultType(EVT VT) const {
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return MVT::i1;
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}
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//===----------------------------------------------------------------------===//
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// Custom DAG Lowering Operations
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//===----------------------------------------------------------------------===//
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SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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case ISD::LOAD: return LowerLOAD(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::AND: return Loweri1ContextSwitch(Op, DAG, ISD::AND);
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IntrinsicID =
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cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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EVT VT = Op.getValueType();
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switch (IntrinsicID) {
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case AMDGPUIntrinsic::SI_vs_load_buffer_index:
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return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
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AMDGPU::VGPR0, VT);
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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}
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break;
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}
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}
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return SDValue();
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}
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/// \brief The function is for lowering i1 operations on the
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/// VCC register.
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///
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/// In the VALU context, VCC is a one bit register, but in the
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/// SALU context the VCC is a 64-bit register (1-bit per thread). Since only
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/// the SALU can perform operations on the VCC register, we need to promote
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/// the operand types from i1 to i64 in order for tablegen to be able to match
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/// this operation to the correct SALU instruction. We do this promotion by
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/// wrapping the operands in a CopyToReg node.
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///
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SDValue SITargetLowering::Loweri1ContextSwitch(SDValue Op,
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SelectionDAG &DAG,
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unsigned VCCNode) const {
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DebugLoc DL = Op.getDebugLoc();
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SDValue OpNode = DAG.getNode(VCCNode, DL, MVT::i64,
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DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i64,
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Op.getOperand(0)),
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DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i64,
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Op.getOperand(1)));
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return DAG.getNode(SIISD::VCC_BITCAST, DL, MVT::i1, OpNode);
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}
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/// \brief Helper function for LowerBRCOND
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static SDNode *findUser(SDValue Value, unsigned Opcode) {
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SDNode *Parent = Value.getNode();
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for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
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I != E; ++I) {
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if (I.getUse().get() != Value)
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continue;
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if (I->getOpcode() == Opcode)
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return *I;
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}
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return 0;
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}
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/// This transforms the control flow intrinsics to get the branch destination as
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/// last parameter, also switches branch target with BR if the need arise
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SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
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SelectionDAG &DAG) const {
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DebugLoc DL = BRCOND.getDebugLoc();
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SDNode *Intr = BRCOND.getOperand(1).getNode();
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SDValue Target = BRCOND.getOperand(2);
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SDNode *BR = 0;
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if (Intr->getOpcode() == ISD::SETCC) {
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// As long as we negate the condition everything is fine
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SDNode *SetCC = Intr;
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assert(SetCC->getConstantOperandVal(1) == 1);
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assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
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ISD::SETNE);
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Intr = SetCC->getOperand(0).getNode();
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} else {
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// Get the target from BR if we don't negate the condition
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BR = findUser(BRCOND, ISD::BR);
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Target = BR->getOperand(1);
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}
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assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
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// Build the result and
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SmallVector<EVT, 4> Res;
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for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
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Res.push_back(Intr->getValueType(i));
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// operands of the new intrinsic call
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SmallVector<SDValue, 4> Ops;
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Ops.push_back(BRCOND.getOperand(0));
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for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
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Ops.push_back(Intr->getOperand(i));
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Ops.push_back(Target);
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// build the new intrinsic call
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SDNode *Result = DAG.getNode(
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Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
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DAG.getVTList(Res.data(), Res.size()), Ops.data(), Ops.size()).getNode();
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if (BR) {
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// Give the branch instruction our target
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SDValue Ops[] = {
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BR->getOperand(0),
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BRCOND.getOperand(2)
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};
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DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops, 2);
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}
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SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
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// Copy the intrinsic results to registers
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for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
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SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
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if (!CopyToReg)
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continue;
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Chain = DAG.getCopyToReg(
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Chain, DL,
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CopyToReg->getOperand(1),
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SDValue(Result, i - 1),
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SDValue());
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DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
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}
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// Remove the old intrinsic from the chain
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DAG.ReplaceAllUsesOfValueWith(
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SDValue(Intr, Intr->getNumValues() - 1),
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Intr->getOperand(0));
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return Chain;
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}
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SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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LoadSDNode *Ptr = dyn_cast<LoadSDNode>(Op);
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assert(Ptr);
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unsigned AddrSpace = Ptr->getPointerInfo().getAddrSpace();
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// We only need to lower USER_SGPR address space loads
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if (AddrSpace != AMDGPUAS::USER_SGPR_ADDRESS) {
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return SDValue();
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}
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// Loads from the USER_SGPR address space can only have constant value
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// pointers.
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ConstantSDNode *BasePtr = dyn_cast<ConstantSDNode>(Ptr->getBasePtr());
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assert(BasePtr);
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unsigned TypeDwordWidth = VT.getSizeInBits() / 32;
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const TargetRegisterClass * dstClass;
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switch (TypeDwordWidth) {
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default:
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assert(!"USER_SGPR value size not implemented");
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return SDValue();
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case 1:
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dstClass = &AMDGPU::SReg_32RegClass;
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break;
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case 2:
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dstClass = &AMDGPU::SReg_64RegClass;
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break;
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}
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uint64_t Index = BasePtr->getZExtValue();
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assert(Index % TypeDwordWidth == 0 && "USER_SGPR not properly aligned");
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unsigned SGPRIndex = Index / TypeDwordWidth;
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unsigned Reg = dstClass->getRegister(SGPRIndex);
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DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
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VT));
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return SDValue();
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}
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SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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SDValue True = Op.getOperand(2);
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SDValue False = Op.getOperand(3);
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SDValue CC = Op.getOperand(4);
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EVT VT = Op.getValueType();
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DebugLoc DL = Op.getDebugLoc();
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// Possible Min/Max pattern
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SDValue MinMax = LowerMinMax(Op, DAG);
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if (MinMax.getNode()) {
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return MinMax;
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}
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SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
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return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
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}
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//===----------------------------------------------------------------------===//
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// Custom DAG optimizations
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//===----------------------------------------------------------------------===//
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SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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DebugLoc DL = N->getDebugLoc();
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EVT VT = N->getValueType(0);
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switch (N->getOpcode()) {
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default: break;
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case ISD::SELECT_CC: {
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N->dump();
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ConstantSDNode *True, *False;
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// i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
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if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
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&& (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
|
|
&& True->isAllOnesValue()
|
|
&& False->isNullValue()
|
|
&& VT == MVT::i1) {
|
|
return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
|
|
N->getOperand(1), N->getOperand(4));
|
|
|
|
}
|
|
break;
|
|
}
|
|
case ISD::SETCC: {
|
|
SDValue Arg0 = N->getOperand(0);
|
|
SDValue Arg1 = N->getOperand(1);
|
|
SDValue CC = N->getOperand(2);
|
|
ConstantSDNode * C = NULL;
|
|
ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
|
|
|
|
// i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
|
|
if (VT == MVT::i1
|
|
&& Arg0.getOpcode() == ISD::SIGN_EXTEND
|
|
&& Arg0.getOperand(0).getValueType() == MVT::i1
|
|
&& (C = dyn_cast<ConstantSDNode>(Arg1))
|
|
&& C->isNullValue()
|
|
&& CCOp == ISD::SETNE) {
|
|
return SimplifySetCC(VT, Arg0.getOperand(0),
|
|
DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
return SDValue();
|
|
}
|
|
|
|
#define NODE_NAME_CASE(node) case SIISD::node: return #node;
|
|
|
|
const char* SITargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
switch (Opcode) {
|
|
default: return AMDGPUTargetLowering::getTargetNodeName(Opcode);
|
|
NODE_NAME_CASE(VCC_AND)
|
|
NODE_NAME_CASE(VCC_BITCAST)
|
|
}
|
|
}
|