Jyotsna Verma 3e1635d08c Hexagon: Add V4 combine instructions and some more Def Pats for V2. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174331 91177308-0d34-0410-b5e6-96231b3b80d8		2013-02-04 15:52:56 +00:00
..
args.ll	Use multiclass to define store instructions with base+immediate offset	2012-12-05 19:32:03 +00:00
combine_ir.ll	Hexagon: Add V4 combine instructions and some more Def Pats for V2.	2013-02-04 15:52:56 +00:00
combine.ll
convertdptoint.ll
convertdptoll.ll
convertsptoint.ll
convertsptoll.ll
dadd.ll
dmul.ll
double.ll
doubleconvert-ieee-rnd-near.ll
dsub.ll
dualstore.ll	Use multiclass to define store instructions with base+immediate offset	2012-12-05 19:32:03 +00:00
fadd.ll
fcmp.ll
float.ll
floatconvert-ieee-rnd-near.ll
fmul.ll
frame.ll
fsub.ll
fusedandshift.ll
idxload-with-zero-offset.ll	Hexagon: Test case to confirm generation of indexed loads with zero offset.	2013-02-01 16:40:06 +00:00
lit.local.cfg
macint.ll
mpy.ll
newvaluejump2.ll
newvaluejump.ll
newvaluestore.ll
opt-fabs.ll
opt-fneg.ll
postinc-load.ll	In hexagon convertToHardwareLoop, don't deref end() iterator	2012-12-07 21:03:15 +00:00
remove_lsr.ll
simpletailcall.ll
static.ll
struct_args_large.ll
struct_args.ll	Hexagon: Add V4 combine instructions and some more Def Pats for V2.	2013-02-04 15:52:56 +00:00
vaddh.ll
validate-offset.ll	Add indexed load/store instructions for offset validation check.	2013-01-17 18:42:37 +00:00