mirror of
https://github.com/c64scene-ar/llvm-6502.git
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13d08bf415
- Add list of physical registers clobbered in pseudo atomic insts Physical registers are clobbered when pseudo atomic instructions are expanded. Add them in clobber list to prevent DAG scheduler to mis-schedule them after these insns are declared side-effect free. - Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173200 91177308-0d34-0410-b5e6-96231b3b80d8
111 lines
5.2 KiB
LLVM
111 lines
5.2 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s
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define void @test(i8** %a, i64* %b, i64 %c, i64 %d) nounwind {
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entry:
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%ptrtoarg4 = load i8** %a, align 8
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%brglist1 = getelementptr i8** %a, i64 1
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%ptrtoarg25 = load i8** %brglist1, align 8
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%0 = load i64* %b, align 8
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%1 = mul i64 %0, 4
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%scevgep = getelementptr i8* %ptrtoarg25, i64 %1
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%2 = mul i64 %d, 4
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br label %loop.cond
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loop.cond: ; preds = %test.exit, %entry
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%asr.iv6 = phi i8* [ %29, %test.exit ], [ %scevgep, %entry ]
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%iv = phi i64 [ %0, %entry ], [ %28, %test.exit ]
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%3 = icmp eq i64 %iv, %c
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br i1 %3, label %return, label %loop
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loop: ; preds = %loop.cond
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%4 = load i64* addrspace(256)* inttoptr (i64 264 to i64* addrspace(256)*), align 8, !tbaa !0
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%5 = load i64* %4, align 8, !tbaa !3
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%vector.size.i = ashr i64 %5, 3
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%num.vector.wi.i = shl i64 %vector.size.i, 3
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%6 = icmp eq i64 %vector.size.i, 0
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br i1 %6, label %scalarIf.i, label %dim_0_vector_pre_head.i
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dim_0_vector_pre_head.i: ; preds = %loop
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%7 = trunc i64 %5 to i32
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%tempvector_func.i = insertelement <8 x i32> undef, i32 %7, i32 0
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%vectorvector_func.i = shufflevector <8 x i32> %tempvector_func.i, <8 x i32> undef, <8 x i32> zeroinitializer
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br label %vector_kernel_entry.i
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vector_kernel_entry.i: ; preds = %vector_kernel_entry.i, %dim_0_vector_pre_head.i
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%asr.iv9 = phi i8* [ %scevgep10, %vector_kernel_entry.i ], [ %asr.iv6, %dim_0_vector_pre_head.i ]
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%asr.iv = phi i64 [ %asr.iv.next, %vector_kernel_entry.i ], [ %vector.size.i, %dim_0_vector_pre_head.i ]
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%8 = bitcast i8* %ptrtoarg4 to i32 addrspace(1)*
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%asr.iv911 = bitcast i8* %asr.iv9 to <8 x i32> addrspace(1)*
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%9 = load <8 x i32> addrspace(1)* %asr.iv911, align 4
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%extract8vector_func.i = extractelement <8 x i32> %9, i32 0
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%extract9vector_func.i = extractelement <8 x i32> %9, i32 1
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%extract10vector_func.i = extractelement <8 x i32> %9, i32 2
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%extract11vector_func.i = extractelement <8 x i32> %9, i32 3
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%extract12vector_func.i = extractelement <8 x i32> %9, i32 4
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%extract13vector_func.i = extractelement <8 x i32> %9, i32 5
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%extract14vector_func.i = extractelement <8 x i32> %9, i32 6
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%extract15vector_func.i = extractelement <8 x i32> %9, i32 7
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%10 = atomicrmw min i32 addrspace(1)* %8, i32 %extract8vector_func.i seq_cst
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%11 = atomicrmw min i32 addrspace(1)* %8, i32 %extract9vector_func.i seq_cst
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%12 = atomicrmw min i32 addrspace(1)* %8, i32 %extract10vector_func.i seq_cst
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%13 = atomicrmw min i32 addrspace(1)* %8, i32 %extract11vector_func.i seq_cst
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%14 = atomicrmw min i32 addrspace(1)* %8, i32 %extract12vector_func.i seq_cst
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%15 = atomicrmw min i32 addrspace(1)* %8, i32 %extract13vector_func.i seq_cst
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%16 = atomicrmw min i32 addrspace(1)* %8, i32 %extract14vector_func.i seq_cst
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%17 = atomicrmw min i32 addrspace(1)* %8, i32 %extract15vector_func.i seq_cst
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store <8 x i32> %vectorvector_func.i, <8 x i32> addrspace(1)* %asr.iv911, align 4
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%asr.iv.next = add i64 %asr.iv, -1
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%scevgep10 = getelementptr i8* %asr.iv9, i64 32
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%dim_0_vector_cmp.to.max.i = icmp eq i64 %asr.iv.next, 0
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br i1 %dim_0_vector_cmp.to.max.i, label %scalarIf.i, label %vector_kernel_entry.i
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scalarIf.i: ; preds = %vector_kernel_entry.i, %loop
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%exec_wi.i = phi i64 [ 0, %loop ], [ %num.vector.wi.i, %vector_kernel_entry.i ]
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%18 = icmp eq i64 %exec_wi.i, %5
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br i1 %18, label %test.exit, label %dim_0_pre_head.i
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dim_0_pre_head.i: ; preds = %scalarIf.i
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%19 = load i64* addrspace(256)* inttoptr (i64 264 to i64* addrspace(256)*), align 8, !tbaa !0
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%20 = load i64* %19, align 8, !tbaa !3
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%21 = trunc i64 %20 to i32
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%22 = mul i64 %vector.size.i, 8
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br label %scalar_kernel_entry.i
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scalar_kernel_entry.i: ; preds = %scalar_kernel_entry.i, %dim_0_pre_head.i
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%asr.iv12 = phi i64 [ %asr.iv.next13, %scalar_kernel_entry.i ], [ %22, %dim_0_pre_head.i ]
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%23 = bitcast i8* %asr.iv6 to i32 addrspace(1)*
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%24 = bitcast i8* %ptrtoarg4 to i32 addrspace(1)*
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%scevgep16 = getelementptr i32 addrspace(1)* %23, i64 %asr.iv12
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%25 = load i32 addrspace(1)* %scevgep16, align 4, !tbaa !4
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%26 = atomicrmw min i32 addrspace(1)* %24, i32 %25 seq_cst
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%scevgep15 = getelementptr i32 addrspace(1)* %23, i64 %asr.iv12
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store i32 %21, i32 addrspace(1)* %scevgep15, align 4, !tbaa !4
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%asr.iv.next13 = add i64 %asr.iv12, 1
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%dim_0_cmp.to.max.i = icmp eq i64 %5, %asr.iv.next13
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br i1 %dim_0_cmp.to.max.i, label %test.exit, label %scalar_kernel_entry.i
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test.exit: ; preds = %scalar_kernel_entry.i, %scalarIf.i
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%27 = bitcast i8* %asr.iv6 to i1*
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%28 = add i64 %iv, %d
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store i64 %28, i64* %b, align 8
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%scevgep8 = getelementptr i1* %27, i64 %2
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%29 = bitcast i1* %scevgep8 to i8*
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br label %loop.cond
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return: ; preds = %loop.cond
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store i64 %0, i64* %b, align 8
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ret void
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}
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!0 = metadata !{metadata !"any pointer", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA"}
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!3 = metadata !{metadata !"long", metadata !1}
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!4 = metadata !{metadata !"int", metadata !1}
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; CHECK: test
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; CHECK: decq
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; CHECK-NOT: cmpxchgl
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; CHECK: jne
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; CHECK: ret
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