mirror of
https://github.com/c64scene-ar/llvm-6502.git
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26d628d6ce
Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230775 91177308-0d34-0410-b5e6-96231b3b80d8
118 lines
2.6 KiB
LLVM
118 lines
2.6 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; Test add with non-legal types
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define void @add_i1(i1 %a, i1 %b) nounwind ssp {
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entry:
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; ARM: add_i1
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; THUMB: add_i1
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%a.addr = alloca i1, align 4
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%0 = add i1 %a, %b
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; ARM: add r0, r0, r1
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; THUMB: add r0, r1
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store i1 %0, i1* %a.addr, align 4
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ret void
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}
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define void @add_i8(i8 %a, i8 %b) nounwind ssp {
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entry:
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; ARM: add_i8
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; THUMB: add_i8
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%a.addr = alloca i8, align 4
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%0 = add i8 %a, %b
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; ARM: add r0, r0, r1
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; THUMB: add r0, r1
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @add_i16(i16 %a, i16 %b) nounwind ssp {
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entry:
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; ARM: add_i16
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; THUMB: add_i16
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%a.addr = alloca i16, align 4
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%0 = add i16 %a, %b
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; ARM: add r0, r0, r1
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; THUMB: add r0, r1
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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; Test or with non-legal types
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define void @or_i1(i1 %a, i1 %b) nounwind ssp {
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entry:
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; ARM: or_i1
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; THUMB: or_i1
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%a.addr = alloca i1, align 4
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%0 = or i1 %a, %b
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; ARM: orr r0, r0, r1
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; THUMB: orrs r0, r1
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store i1 %0, i1* %a.addr, align 4
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ret void
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}
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define void @or_i8(i8 %a, i8 %b) nounwind ssp {
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entry:
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; ARM: or_i8
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; THUMB: or_i8
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%a.addr = alloca i8, align 4
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%0 = or i8 %a, %b
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; ARM: orr r0, r0, r1
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; THUMB: orrs r0, r1
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @or_i16(i16 %a, i16 %b) nounwind ssp {
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entry:
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; ARM: or_i16
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; THUMB: or_i16
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%a.addr = alloca i16, align 4
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%0 = or i16 %a, %b
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; ARM: orr r0, r0, r1
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; THUMB: orrs r0, r1
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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; Test sub with non-legal types
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define void @sub_i1(i1 %a, i1 %b) nounwind ssp {
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entry:
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; ARM: sub_i1
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; THUMB: sub_i1
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%a.addr = alloca i1, align 4
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%0 = sub i1 %a, %b
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; ARM: sub r0, r0, r1
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; THUMB: subs r0, r0, r1
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store i1 %0, i1* %a.addr, align 4
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ret void
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}
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define void @sub_i8(i8 %a, i8 %b) nounwind ssp {
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entry:
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; ARM: sub_i8
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; THUMB: sub_i8
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%a.addr = alloca i8, align 4
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%0 = sub i8 %a, %b
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; ARM: sub r0, r0, r1
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; THUMB: subs r0, r0, r1
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @sub_i16(i16 %a, i16 %b) nounwind ssp {
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entry:
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; ARM: sub_i16
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; THUMB: sub_i16
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%a.addr = alloca i16, align 4
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%0 = sub i16 %a, %b
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; ARM: sub r0, r0, r1
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; THUMB: subs r0, r0, r1
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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