Quentin Colombet b0f8afd43c Fix an over-constrained assertion in MachineFunction::addLiveIn. ... The assertion was checking that the virtual register VReg used to represent the physical register PReg uses the same register class as the one passed to MachineFunction::addLiveIn. This is over-constraining because it is sufficient to check that the register class of VReg (VRegRC) is a subclass of the register class of PReg (PRegRC) and that VRegRC contains PReg. Indeed, if VReg gets constrained because of some operation constraints between two calls of MachineFunction::addLiveIn, the original assertion cannot match. This fixes <rdar://problem/15633429>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197097 91177308-0d34-0410-b5e6-96231b3b80d8		2013-12-12 00:15:47 +00:00
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AArch64	Fix an over-constrained assertion in MachineFunction::addLiveIn.	2013-12-12 00:15:47 +00:00
ARM	ARM: constrain register-class in fast-isel	2013-12-11 16:04:57 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Distinguish and choose 16 or 32 bit forms of save/restore for Mips16.	2013-12-11 03:32:44 +00:00
MSP430
NVPTX	[NVPTX] Fix off-by-one error when creating the VT list for an SDNode	2013-12-05 12:58:00 +00:00
PowerPC	Fix the PPC subsumes-predicate check	2013-12-11 23:12:25 +00:00
R600	R600/SI: Add i64 cmp tests	2013-12-10 21:11:55 +00:00
SPARC	[SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9.	2013-12-09 05:13:25 +00:00
SystemZ	[SystemZ] Optimize fcmp X, 0 in cases where X is also negated	2013-12-11 11:45:08 +00:00
Thumb	Use FileCheck and expand the test a bit.	2013-11-27 19:22:14 +00:00
Thumb2	Add support for parsing ARM symbol variants on ELF targets	2013-12-04 22:43:20 +00:00
X86	On ELF and COFF treat linker_private like private.	2013-12-11 22:18:44 +00:00
XCore	XCore target: Make handling of large frames not dependent upon an FP.	2013-12-02 11:05:28 +00:00