mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 04:30:23 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
557 lines
17 KiB
LLVM
557 lines
17 KiB
LLVM
; RUN: opt -S -simplifycfg < %s | FileCheck -check-prefix=CHECK %s
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; RUN: opt -S -default-data-layout="p:32:32-p1:16:16" -simplifycfg < %s | FileCheck -check-prefix=CHECK -check-prefix=DL %s
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declare void @foo1()
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declare void @foo2()
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define void @test1(i32 %V) {
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%C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1]
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%C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1]
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%CN = or i1 %C1, %C2 ; <i1> [#uses=1]
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br i1 %CN, label %T, label %F
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T: ; preds = %0
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call void @foo1( )
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ret void
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F: ; preds = %0
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call void @foo2( )
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ret void
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; CHECK-LABEL: @test1(
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; CHECK: switch i32 %V, label %F [
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; CHECK: i32 17, label %T
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; CHECK: i32 4, label %T
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; CHECK: ]
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}
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define void @test1_ptr(i32* %V) {
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%C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
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%C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
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%CN = or i1 %C1, %C2 ; <i1> [#uses=1]
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br i1 %CN, label %T, label %F
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T: ; preds = %0
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call void @foo1( )
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ret void
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F: ; preds = %0
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call void @foo2( )
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ret void
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; CHECK-LABEL: @test1_ptr(
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; DL: %magicptr = ptrtoint i32* %V to i32
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; DL: switch i32 %magicptr, label %F [
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; DL: i32 17, label %T
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; DL: i32 4, label %T
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; DL: ]
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}
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define void @test1_ptr_as1(i32 addrspace(1)* %V) {
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%C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
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%C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
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%CN = or i1 %C1, %C2 ; <i1> [#uses=1]
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br i1 %CN, label %T, label %F
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T: ; preds = %0
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call void @foo1( )
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ret void
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F: ; preds = %0
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call void @foo2( )
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ret void
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; CHECK-LABEL: @test1_ptr_as1(
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; DL: %magicptr = ptrtoint i32 addrspace(1)* %V to i16
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; DL: switch i16 %magicptr, label %F [
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; DL: i16 17, label %T
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; DL: i16 4, label %T
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; DL: ]
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}
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define void @test2(i32 %V) {
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%C1 = icmp ne i32 %V, 4 ; <i1> [#uses=1]
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%C2 = icmp ne i32 %V, 17 ; <i1> [#uses=1]
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%CN = and i1 %C1, %C2 ; <i1> [#uses=1]
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br i1 %CN, label %T, label %F
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T: ; preds = %0
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call void @foo1( )
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ret void
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F: ; preds = %0
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call void @foo2( )
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ret void
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; CHECK-LABEL: @test2(
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; CHECK: switch i32 %V, label %T [
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; CHECK: i32 17, label %F
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; CHECK: i32 4, label %F
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; CHECK: ]
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}
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define void @test3(i32 %V) {
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%C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1]
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br i1 %C1, label %T, label %N
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N: ; preds = %0
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%C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1]
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br i1 %C2, label %T, label %F
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T: ; preds = %N, %0
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call void @foo1( )
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ret void
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F: ; preds = %N
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call void @foo2( )
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ret void
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; CHECK-LABEL: @test3(
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; CHECK: switch i32 %V, label %F [
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; CHECK: i32 4, label %T
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; CHECK: i32 17, label %T
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; CHECK: ]
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}
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define i32 @test4(i8 zeroext %c) nounwind ssp noredzone {
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entry:
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%cmp = icmp eq i8 %c, 62
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br i1 %cmp, label %lor.end, label %lor.lhs.false
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lor.lhs.false: ; preds = %entry
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%cmp4 = icmp eq i8 %c, 34
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br i1 %cmp4, label %lor.end, label %lor.rhs
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lor.rhs: ; preds = %lor.lhs.false
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%cmp8 = icmp eq i8 %c, 92
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br label %lor.end
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lor.end: ; preds = %lor.rhs, %lor.lhs.false, %entry
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%0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp8, %lor.rhs ]
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%lor.ext = zext i1 %0 to i32
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ret i32 %lor.ext
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; CHECK-LABEL: @test4(
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; CHECK: switch i8 %c, label %lor.rhs [
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; CHECK: i8 62, label %lor.end
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; CHECK: i8 34, label %lor.end
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; CHECK: i8 92, label %lor.end
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; CHECK: ]
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}
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define i32 @test5(i8 zeroext %c) nounwind ssp noredzone {
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entry:
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switch i8 %c, label %lor.rhs [
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i8 62, label %lor.end
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i8 34, label %lor.end
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i8 92, label %lor.end
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]
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lor.rhs: ; preds = %entry
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%V = icmp eq i8 %c, 92
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br label %lor.end
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lor.end: ; preds = %entry, %entry, %entry, %lor.rhs
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%0 = phi i1 [ true, %entry ], [ %V, %lor.rhs ], [ true, %entry ], [ true, %entry ]
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%lor.ext = zext i1 %0 to i32
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ret i32 %lor.ext
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; CHECK-LABEL: @test5(
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; CHECK: switch i8 %c, label %lor.rhs [
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; CHECK: i8 62, label %lor.end
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; CHECK: i8 34, label %lor.end
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; CHECK: i8 92, label %lor.end
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; CHECK: ]
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}
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define i1 @test6({ i32, i32 }* %I) {
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entry:
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%tmp.1.i = getelementptr { i32, i32 }, { i32, i32 }* %I, i64 0, i32 1 ; <i32*> [#uses=1]
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%tmp.2.i = load i32, i32* %tmp.1.i ; <i32> [#uses=6]
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%tmp.2 = icmp eq i32 %tmp.2.i, 14 ; <i1> [#uses=1]
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br i1 %tmp.2, label %shortcirc_done.4, label %shortcirc_next.0
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shortcirc_next.0: ; preds = %entry
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%tmp.6 = icmp eq i32 %tmp.2.i, 15 ; <i1> [#uses=1]
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br i1 %tmp.6, label %shortcirc_done.4, label %shortcirc_next.1
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shortcirc_next.1: ; preds = %shortcirc_next.0
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%tmp.11 = icmp eq i32 %tmp.2.i, 16 ; <i1> [#uses=1]
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br i1 %tmp.11, label %shortcirc_done.4, label %shortcirc_next.2
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shortcirc_next.2: ; preds = %shortcirc_next.1
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%tmp.16 = icmp eq i32 %tmp.2.i, 17 ; <i1> [#uses=1]
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br i1 %tmp.16, label %shortcirc_done.4, label %shortcirc_next.3
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shortcirc_next.3: ; preds = %shortcirc_next.2
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%tmp.21 = icmp eq i32 %tmp.2.i, 18 ; <i1> [#uses=1]
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br i1 %tmp.21, label %shortcirc_done.4, label %shortcirc_next.4
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shortcirc_next.4: ; preds = %shortcirc_next.3
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%tmp.26 = icmp eq i32 %tmp.2.i, 19 ; <i1> [#uses=1]
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br label %UnifiedReturnBlock
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shortcirc_done.4: ; preds = %shortcirc_next.3, %shortcirc_next.2, %shortcirc_next.1, %shortcirc_next.0, %entry
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br label %UnifiedReturnBlock
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UnifiedReturnBlock: ; preds = %shortcirc_done.4, %shortcirc_next.4
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%UnifiedRetVal = phi i1 [ %tmp.26, %shortcirc_next.4 ], [ true, %shortcirc_done.4 ] ; <i1> [#uses=1]
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ret i1 %UnifiedRetVal
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; CHECK-LABEL: @test6(
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; CHECK: %tmp.2.i.off = add i32 %tmp.2.i, -14
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; CHECK: %switch = icmp ult i32 %tmp.2.i.off, 6
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}
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define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
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entry:
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%cmp = icmp ult i32 %x, 32
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%cmp4 = icmp eq i8 %c, 97
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%or.cond = or i1 %cmp, %cmp4
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%cmp9 = icmp eq i8 %c, 99
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%or.cond11 = or i1 %or.cond, %cmp9
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br i1 %or.cond11, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @foo1() nounwind noredzone
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ret void
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if.end: ; preds = %entry
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ret void
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; CHECK-LABEL: @test7(
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; CHECK: %cmp = icmp ult i32 %x, 32
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; CHECK: br i1 %cmp, label %if.then, label %switch.early.test
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; CHECK: switch.early.test:
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; CHECK: switch i8 %c, label %if.end [
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; CHECK: i8 99, label %if.then
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; CHECK: i8 97, label %if.then
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; CHECK: ]
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}
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define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
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entry:
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br i1 %C, label %N, label %if.then
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N:
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%cmp = icmp ult i32 %x, 32
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%cmp4 = icmp eq i8 %c, 97
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%or.cond = or i1 %cmp, %cmp4
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%cmp9 = icmp eq i8 %c, 99
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%or.cond11 = or i1 %or.cond, %cmp9
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br i1 %or.cond11, label %if.then, label %if.end
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if.then: ; preds = %entry
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%A = phi i32 [0, %entry], [42, %N]
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tail call void @foo1() nounwind noredzone
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ret i32 %A
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if.end: ; preds = %entry
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ret i32 0
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; CHECK-LABEL: @test8(
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; CHECK: switch.early.test:
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; CHECK: switch i8 %c, label %if.end [
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; CHECK: i8 99, label %if.then
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; CHECK: i8 97, label %if.then
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; CHECK: ]
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; CHECK: %A = phi i32 [ 0, %entry ], [ 42, %switch.early.test ], [ 42, %N ], [ 42, %switch.early.test ]
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}
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;; This is "Example 7" from http://blog.regehr.org/archives/320
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define i32 @test9(i8 zeroext %c) nounwind ssp noredzone {
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entry:
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%cmp = icmp ult i8 %c, 33
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br i1 %cmp, label %lor.end, label %lor.lhs.false
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lor.lhs.false: ; preds = %entry
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%cmp4 = icmp eq i8 %c, 46
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br i1 %cmp4, label %lor.end, label %lor.lhs.false6
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lor.lhs.false6: ; preds = %lor.lhs.false
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%cmp9 = icmp eq i8 %c, 44
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br i1 %cmp9, label %lor.end, label %lor.lhs.false11
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lor.lhs.false11: ; preds = %lor.lhs.false6
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%cmp14 = icmp eq i8 %c, 58
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br i1 %cmp14, label %lor.end, label %lor.lhs.false16
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lor.lhs.false16: ; preds = %lor.lhs.false11
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%cmp19 = icmp eq i8 %c, 59
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br i1 %cmp19, label %lor.end, label %lor.lhs.false21
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lor.lhs.false21: ; preds = %lor.lhs.false16
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%cmp24 = icmp eq i8 %c, 60
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br i1 %cmp24, label %lor.end, label %lor.lhs.false26
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lor.lhs.false26: ; preds = %lor.lhs.false21
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%cmp29 = icmp eq i8 %c, 62
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br i1 %cmp29, label %lor.end, label %lor.lhs.false31
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lor.lhs.false31: ; preds = %lor.lhs.false26
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%cmp34 = icmp eq i8 %c, 34
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br i1 %cmp34, label %lor.end, label %lor.lhs.false36
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lor.lhs.false36: ; preds = %lor.lhs.false31
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%cmp39 = icmp eq i8 %c, 92
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br i1 %cmp39, label %lor.end, label %lor.rhs
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lor.rhs: ; preds = %lor.lhs.false36
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%cmp43 = icmp eq i8 %c, 39
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br label %lor.end
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lor.end: ; preds = %lor.rhs, %lor.lhs.false36, %lor.lhs.false31, %lor.lhs.false26, %lor.lhs.false21, %lor.lhs.false16, %lor.lhs.false11, %lor.lhs.false6, %lor.lhs.false, %entry
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%0 = phi i1 [ true, %lor.lhs.false36 ], [ true, %lor.lhs.false31 ], [ true, %lor.lhs.false26 ], [ true, %lor.lhs.false21 ], [ true, %lor.lhs.false16 ], [ true, %lor.lhs.false11 ], [ true, %lor.lhs.false6 ], [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp43, %lor.rhs ]
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%conv46 = zext i1 %0 to i32
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ret i32 %conv46
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; CHECK-LABEL: @test9(
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; CHECK: %cmp = icmp ult i8 %c, 33
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; CHECK: br i1 %cmp, label %lor.end, label %switch.early.test
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; CHECK: switch.early.test:
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; CHECK: switch i8 %c, label %lor.rhs [
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; CHECK: i8 92, label %lor.end
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; CHECK: i8 62, label %lor.end
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; CHECK: i8 60, label %lor.end
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; CHECK: i8 59, label %lor.end
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; CHECK: i8 58, label %lor.end
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; CHECK: i8 46, label %lor.end
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; CHECK: i8 44, label %lor.end
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; CHECK: i8 34, label %lor.end
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; CHECK: i8 39, label %lor.end
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; CHECK: ]
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}
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define i32 @test10(i32 %mode, i1 %Cond) {
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%A = icmp ne i32 %mode, 0
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%B = icmp ne i32 %mode, 51
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%C = and i1 %A, %B
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%D = and i1 %C, %Cond
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br i1 %D, label %T, label %F
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T:
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ret i32 123
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F:
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ret i32 324
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; CHECK-LABEL: @test10(
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; CHECK: br i1 %Cond, label %switch.early.test, label %F
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; CHECK:switch.early.test:
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; CHECK: switch i32 %mode, label %T [
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; CHECK: i32 51, label %F
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; CHECK: i32 0, label %F
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; CHECK: ]
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}
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; PR8780
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define i32 @test11(i32 %bar) nounwind {
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entry:
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%cmp = icmp eq i32 %bar, 4
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%cmp2 = icmp eq i32 %bar, 35
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%or.cond = or i1 %cmp, %cmp2
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%cmp5 = icmp eq i32 %bar, 53
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%or.cond1 = or i1 %or.cond, %cmp5
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%cmp8 = icmp eq i32 %bar, 24
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%or.cond2 = or i1 %or.cond1, %cmp8
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%cmp11 = icmp eq i32 %bar, 23
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%or.cond3 = or i1 %or.cond2, %cmp11
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%cmp14 = icmp eq i32 %bar, 55
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%or.cond4 = or i1 %or.cond3, %cmp14
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%cmp17 = icmp eq i32 %bar, 12
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%or.cond5 = or i1 %or.cond4, %cmp17
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%cmp20 = icmp eq i32 %bar, 35
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%or.cond6 = or i1 %or.cond5, %cmp20
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br i1 %or.cond6, label %if.then, label %if.end
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if.then: ; preds = %entry
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br label %return
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if.end: ; preds = %entry
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br label %return
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return: ; preds = %if.end, %if.then
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%retval.0 = phi i32 [ 1, %if.then ], [ 0, %if.end ]
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ret i32 %retval.0
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; CHECK-LABEL: @test11(
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; CHECK: switch i32 %bar, label %if.end [
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; CHECK: i32 55, label %return
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; CHECK: i32 53, label %return
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; CHECK: i32 35, label %return
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; CHECK: i32 24, label %return
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; CHECK: i32 23, label %return
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; CHECK: i32 12, label %return
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; CHECK: i32 4, label %return
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; CHECK: ]
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}
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define void @test12() nounwind {
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entry:
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br label %bb49.us.us
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bb49.us.us:
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%A = icmp eq i32 undef, undef
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br i1 %A, label %bb55.us.us, label %malformed
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bb48.us.us:
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%B = icmp ugt i32 undef, undef
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br i1 %B, label %bb55.us.us, label %bb49.us.us
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bb55.us.us:
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br label %bb48.us.us
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malformed:
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ret void
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; CHECK-LABEL: @test12(
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}
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; test13 - handle switch formation with ult.
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define void @test13(i32 %x) nounwind ssp noredzone {
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entry:
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%cmp = icmp ult i32 %x, 2
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br i1 %cmp, label %if.then, label %lor.lhs.false3
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lor.lhs.false3: ; preds = %lor.lhs.false
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%cmp5 = icmp eq i32 %x, 3
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br i1 %cmp5, label %if.then, label %lor.lhs.false6
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lor.lhs.false6: ; preds = %lor.lhs.false3
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%cmp8 = icmp eq i32 %x, 4
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br i1 %cmp8, label %if.then, label %lor.lhs.false9
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lor.lhs.false9: ; preds = %lor.lhs.false6
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%cmp11 = icmp eq i32 %x, 6
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br i1 %cmp11, label %if.then, label %if.end
|
|
|
|
if.then: ; preds = %lor.lhs.false9, %lor.lhs.false6, %lor.lhs.false3, %lor.lhs.false, %entry
|
|
call void @foo1() noredzone
|
|
br label %if.end
|
|
|
|
if.end: ; preds = %if.then, %lor.lhs.false9
|
|
ret void
|
|
; CHECK-LABEL: @test13(
|
|
; CHECK: switch i32 %x, label %if.end [
|
|
; CHECK: i32 6, label %if.then
|
|
; CHECK: i32 4, label %if.then
|
|
; CHECK: i32 3, label %if.then
|
|
; CHECK: i32 1, label %if.then
|
|
; CHECK: i32 0, label %if.then
|
|
; CHECK: ]
|
|
}
|
|
|
|
; test14 - handle switch formation with ult.
|
|
define void @test14(i32 %x) nounwind ssp noredzone {
|
|
entry:
|
|
%cmp = icmp ugt i32 %x, 2
|
|
br i1 %cmp, label %lor.lhs.false3, label %if.then
|
|
|
|
lor.lhs.false3: ; preds = %lor.lhs.false
|
|
%cmp5 = icmp ne i32 %x, 3
|
|
br i1 %cmp5, label %lor.lhs.false6, label %if.then
|
|
|
|
lor.lhs.false6: ; preds = %lor.lhs.false3
|
|
%cmp8 = icmp ne i32 %x, 4
|
|
br i1 %cmp8, label %lor.lhs.false9, label %if.then
|
|
|
|
lor.lhs.false9: ; preds = %lor.lhs.false6
|
|
%cmp11 = icmp ne i32 %x, 6
|
|
br i1 %cmp11, label %if.end, label %if.then
|
|
|
|
if.then: ; preds = %lor.lhs.false9, %lor.lhs.false6, %lor.lhs.false3, %lor.lhs.false, %entry
|
|
call void @foo1() noredzone
|
|
br label %if.end
|
|
|
|
if.end: ; preds = %if.then, %lor.lhs.false9
|
|
ret void
|
|
; CHECK-LABEL: @test14(
|
|
; CHECK: switch i32 %x, label %if.end [
|
|
; CHECK: i32 6, label %if.then
|
|
; CHECK: i32 4, label %if.then
|
|
; CHECK: i32 3, label %if.then
|
|
; CHECK: i32 1, label %if.then
|
|
; CHECK: i32 0, label %if.then
|
|
; CHECK: ]
|
|
}
|
|
|
|
; Don't crash on ginormous ranges.
|
|
define void @test15(i128 %x) nounwind {
|
|
%cmp = icmp ugt i128 %x, 2
|
|
br i1 %cmp, label %if.end, label %lor.false
|
|
|
|
lor.false:
|
|
%cmp2 = icmp ne i128 %x, 100000000000000000000
|
|
br i1 %cmp2, label %if.end, label %if.then
|
|
|
|
if.then:
|
|
call void @foo1() noredzone
|
|
br label %if.end
|
|
|
|
if.end:
|
|
ret void
|
|
|
|
; CHECK-LABEL: @test15(
|
|
; CHECK-NOT: switch
|
|
; CHECK: ret void
|
|
}
|
|
|
|
; PR8675
|
|
; rdar://5134905
|
|
define zeroext i1 @test16(i32 %x) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: @test16(
|
|
; CHECK: %x.off = add i32 %x, -1
|
|
; CHECK: %switch = icmp ult i32 %x.off, 3
|
|
%cmp.i = icmp eq i32 %x, 1
|
|
br i1 %cmp.i, label %lor.end, label %lor.lhs.false
|
|
|
|
lor.lhs.false:
|
|
%cmp.i2 = icmp eq i32 %x, 2
|
|
br i1 %cmp.i2, label %lor.end, label %lor.rhs
|
|
|
|
lor.rhs:
|
|
%cmp.i1 = icmp eq i32 %x, 3
|
|
br label %lor.end
|
|
|
|
lor.end:
|
|
%0 = phi i1 [ true, %lor.lhs.false ], [ true, %entry ], [ %cmp.i1, %lor.rhs ]
|
|
ret i1 %0
|
|
}
|
|
|
|
; Check that we don't turn an icmp into a switch where it's not useful.
|
|
define void @test17(i32 %x, i32 %y) {
|
|
%cmp = icmp ult i32 %x, 3
|
|
%switch = icmp ult i32 %y, 2
|
|
%or.cond775 = or i1 %cmp, %switch
|
|
br i1 %or.cond775, label %lor.lhs.false8, label %return
|
|
|
|
lor.lhs.false8:
|
|
tail call void @foo1()
|
|
ret void
|
|
|
|
return:
|
|
ret void
|
|
|
|
; CHECK-LABEL: @test17(
|
|
; CHECK-NOT: switch.early.test
|
|
; CHECK-NOT: switch i32
|
|
; CHECK: ret void
|
|
}
|
|
|
|
define void @test18(i32 %arg) {
|
|
bb:
|
|
%tmp = and i32 %arg, -2
|
|
%tmp1 = icmp eq i32 %tmp, 8
|
|
%tmp2 = icmp eq i32 %arg, 10
|
|
%tmp3 = or i1 %tmp1, %tmp2
|
|
%tmp4 = icmp eq i32 %arg, 11
|
|
%tmp5 = or i1 %tmp3, %tmp4
|
|
%tmp6 = icmp eq i32 %arg, 12
|
|
%tmp7 = or i1 %tmp5, %tmp6
|
|
br i1 %tmp7, label %bb19, label %bb8
|
|
|
|
bb8: ; preds = %bb
|
|
%tmp9 = add i32 %arg, -13
|
|
%tmp10 = icmp ult i32 %tmp9, 2
|
|
%tmp11 = icmp eq i32 %arg, 16
|
|
%tmp12 = or i1 %tmp10, %tmp11
|
|
%tmp13 = icmp eq i32 %arg, 17
|
|
%tmp14 = or i1 %tmp12, %tmp13
|
|
%tmp15 = icmp eq i32 %arg, 18
|
|
%tmp16 = or i1 %tmp14, %tmp15
|
|
%tmp17 = icmp eq i32 %arg, 15
|
|
%tmp18 = or i1 %tmp16, %tmp17
|
|
br i1 %tmp18, label %bb19, label %bb20
|
|
|
|
bb19: ; preds = %bb8, %bb
|
|
tail call void @foo1()
|
|
br label %bb20
|
|
|
|
bb20: ; preds = %bb19, %bb8
|
|
ret void
|
|
|
|
; CHECK-LABEL: @test18(
|
|
; CHECK: %arg.off = add i32 %arg, -8
|
|
; CHECK: icmp ult i32 %arg.off, 11
|
|
}
|