mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-11 10:31:40 +00:00
2c68cde701
This fix changes the parameters #r and #s that are passed to the UBFM/SBFM instruction to get the zero/sign-extension for free. The original problem was that the shift left would use the 32-bit shift even for i8/i16 value types, which could leave the upper bits set with "garbage" values. The arithmetic shift right on the other side would use the wrong MSB as sign-bit to determine what bits to shift into the value. This fixes <rdar://problem/17907720>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214788 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
2.2 KiB
LLVM
100 lines
2.2 KiB
LLVM
; RUN: llc -fast-isel -fast-isel-abort -mtriple=arm64-apple-darwin < %s | FileCheck %s
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; CHECK-LABEL: lsl_i8
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; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define zeroext i8 @lsl_i8(i8 %a) {
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%1 = shl i8 %a, 4
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ret i8 %1
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}
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; CHECK-LABEL: lsl_i16
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; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
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define zeroext i16 @lsl_i16(i16 %a) {
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%1 = shl i16 %a, 8
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ret i16 %1
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}
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; CHECK-LABEL: lsl_i32
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; CHECK: lsl {{w[0-9]*}}, {{w[0-9]*}}, #16
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define zeroext i32 @lsl_i32(i32 %a) {
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%1 = shl i32 %a, 16
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ret i32 %1
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}
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; FIXME: This shouldn't use the variable shift version.
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; CHECK-LABEL: lsl_i64
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; CHECK: lsl {{x[0-9]*}}, {{x[0-9]*}}, {{x[0-9]*}}
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define i64 @lsl_i64(i64 %a) {
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%1 = shl i64 %a, 32
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ret i64 %1
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}
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; CHECK-LABEL: lsr_i8
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; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define zeroext i8 @lsr_i8(i8 %a) {
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%1 = lshr i8 %a, 4
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ret i8 %1
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}
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; CHECK-LABEL: lsr_i16
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; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
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define zeroext i16 @lsr_i16(i16 %a) {
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%1 = lshr i16 %a, 8
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ret i16 %1
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}
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; CHECK-LABEL: lsr_i32
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; CHECK: lsr {{w[0-9]*}}, {{w[0-9]*}}, #16
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define zeroext i32 @lsr_i32(i32 %a) {
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%1 = lshr i32 %a, 16
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ret i32 %1
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}
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; FIXME: This shouldn't use the variable shift version.
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; CHECK-LABEL: lsr_i64
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; CHECK: lsr {{x[0-9]*}}, {{x[0-9]*}}, {{x[0-9]*}}
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define i64 @lsr_i64(i64 %a) {
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%1 = lshr i64 %a, 32
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ret i64 %1
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}
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; CHECK-LABEL: asr_i8
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; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define zeroext i8 @asr_i8(i8 %a) {
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%1 = ashr i8 %a, 4
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ret i8 %1
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}
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; CHECK-LABEL: asr_i16
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; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
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define zeroext i16 @asr_i16(i16 %a) {
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%1 = ashr i16 %a, 8
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ret i16 %1
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}
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; CHECK-LABEL: asr_i32
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; CHECK: asr {{w[0-9]*}}, {{w[0-9]*}}, #16
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define zeroext i32 @asr_i32(i32 %a) {
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%1 = ashr i32 %a, 16
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ret i32 %1
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}
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; FIXME: This shouldn't use the variable shift version.
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; CHECK-LABEL: asr_i64
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; CHECK: asr {{x[0-9]*}}, {{x[0-9]*}}, {{x[0-9]*}}
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define i64 @asr_i64(i64 %a) {
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%1 = ashr i64 %a, 32
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ret i64 %1
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}
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; CHECK-LABEL: shift_test1
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; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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; CHECK-NEXT: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
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define i32 @shift_test1(i8 %a) {
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%1 = shl i8 %a, 4
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%2 = ashr i8 %1, 4
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%3 = sext i8 %2 to i32
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ret i32 %3
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}
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