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Custom lower AND, OR, XOR bitwise operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60098 91177308-0d34-0410-b5e6-96231b3b80d8
328 lines
12 KiB
TableGen
328 lines
12 KiB
TableGen
//===- PIC16InstrInfo.td - PIC16 Instruction defs -------------*- tblgen-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the ARM instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// PIC16 Specific Type Constraints.
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//===----------------------------------------------------------------------===//
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class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
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class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
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//===----------------------------------------------------------------------===//
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// PIC16 Specific Type Profiles.
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//===----------------------------------------------------------------------===//
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// Generic type profiles for i8/i16 unary/binary operations.
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// Taking one i8 or i16 and producing void.
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def SDTI8VoidOp : SDTypeProfile<0, 1, [SDTCisI8<0>]>;
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def SDTI16VoidOp : SDTypeProfile<0, 1, [SDTCisI16<0>]>;
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// Taking one value and producing an output of same type.
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def SDTI8UnaryOp : SDTypeProfile<1, 1, [SDTCisI8<0>, SDTCisI8<1>]>;
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def SDTI16UnaryOp : SDTypeProfile<1, 1, [SDTCisI16<0>, SDTCisI16<1>]>;
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// Taking two values and producing an output of same type.
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def SDTI8BinOp : SDTypeProfile<1, 2, [SDTCisI8<0>, SDTCisI8<1>, SDTCisI8<2>]>;
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def SDTI16BinOp : SDTypeProfile<1, 2, [SDTCisI16<0>, SDTCisI16<1>,
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SDTCisI16<2>]>;
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// Node specific type profiles.
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def SDT_PIC16Load : SDTypeProfile<1, 3, [SDTCisI8<0>, SDTCisI8<1>,
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SDTCisI8<2>, SDTCisI8<3>]>;
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def SDT_PIC16Store : SDTypeProfile<0, 4, [SDTCisI8<0>, SDTCisI8<1>,
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SDTCisI8<2>, SDTCisI8<3>]>;
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//===----------------------------------------------------------------------===//
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// PIC16 addressing modes matching via DAG.
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//===----------------------------------------------------------------------===//
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def diraddr : ComplexPattern<i8, 1, "SelectDirectAddr", [], []>;
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//===----------------------------------------------------------------------===//
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// PIC16 Specific Node Definitions.
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//===----------------------------------------------------------------------===//
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def PIC16callseq_start : SDNode<"ISD::CALLSEQ_START", SDTI8VoidOp,
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[SDNPHasChain, SDNPOutFlag]>;
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def PIC16callseq_end : SDNode<"ISD::CALLSEQ_END", SDTI8VoidOp,
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[SDNPHasChain, SDNPOutFlag]>;
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// Low 8-bits of GlobalAddress.
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def PIC16Lo : SDNode<"PIC16ISD::Lo", SDTI8UnaryOp>;
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// High 8-bits of GlobalAddress.
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def PIC16Hi : SDNode<"PIC16ISD::Hi", SDTI8UnaryOp>;
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// The MTHI and MTLO nodes are used only to match them in the incoming
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// DAG for replacement by corresponding set_fsrhi, set_fsrlo insntructions.
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// These nodes are not used for defining any instructions.
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def MTLO : SDNode<"PIC16ISD::MTLO", SDTI8UnaryOp>;
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def MTHI : SDNode<"PIC16ISD::MTHI", SDTI8UnaryOp>;
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// Node to generate Bank Select for a GlobalAddress.
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def Banksel : SDNode<"PIC16ISD::Banksel", SDTI8UnaryOp>;
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// Node to match a direct store operation.
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def PIC16Store : SDNode<"PIC16ISD::PIC16Store", SDT_PIC16Store, [SDNPHasChain]>;
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// Node to match a direct load operation.
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def PIC16Load : SDNode<"PIC16ISD::PIC16Load", SDT_PIC16Load, [SDNPHasChain]>;
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// Nodes to match bitwise operatios.
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def OR : SDNode<"ISD::OR", SDTI8BinOp>;
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def XOR : SDNode<"ISD::XOR", SDTI8BinOp>;
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def AND : SDNode<"ISD::AND", SDTI8BinOp>;
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//===----------------------------------------------------------------------===//
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// PIC16 Operand Definitions.
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//===----------------------------------------------------------------------===//
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def i8mem : Operand<i8>;
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include "PIC16InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// PIC16 Common Classes.
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//===----------------------------------------------------------------------===//
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// W = W Op F : Load the value from F and do Op to W
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class BinOpFW<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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ByteFormat<OpCode, (outs GPR:$dst),
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(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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!strconcat(OpcStr, " $ptrlo + $offset, W"),
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[(set GPR:$dst, (OpNode GPR:$src, (PIC16Load diraddr:$ptrlo,
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(i8 imm:$ptrhi),
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(i8 imm:$offset))))]>;
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// F = F Op W : Load the value from F, do op with W and store in F
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class BinOpWF<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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ByteFormat<OpCode, (outs),
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(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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!strconcat(OpcStr, " $ptrlo + $offset"),
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[(PIC16Store (OpNode GPR:$src, (PIC16Load diraddr:$ptrlo,
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(i8 imm:$ptrhi),
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(i8 imm:$offset))),
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diraddr:$ptrlo,
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(i8 imm:$ptrhi), (i8 imm:$offset)
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)]>;
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//===----------------------------------------------------------------------===//
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// PIC16 Instructions.
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions.
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i8imm:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(PIC16callseq_start imm:$amt)]>;
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def ADJCALLSTACKUP : Pseudo<(outs), (ins i8imm:$amt),
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"!ADJCALLSTACKUP $amt",
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[(PIC16callseq_end imm:$amt)]>;
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//-----------------------------------
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// Vaious movlw insn patterns.
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//-----------------------------------
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let isReMaterializable = 1 in {
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// Move 8-bit literal to W.
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def movlw : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src),
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"movlw $src",
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[(set GPR:$dst, (i8 imm:$src))]>;
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// Move a Lo(TGA) to W.
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def movlw_lo : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src),
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"movlw LOW(${src})",
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[(set GPR:$dst, (PIC16Lo tglobaladdr:$src))]>;
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// Move a Hi(TGA) to W.
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def movlw_hi : BitFormat<12, (outs GPR:$dst), (ins i8imm:$src),
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"movlw HIGH(${src})",
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[(set GPR:$dst, (PIC16Hi tglobaladdr:$src))]>;
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}
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//-------------------
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// FSR setting insns.
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//-------------------
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// These insns are matched via a DAG replacement pattern.
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def set_fsrlo:
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ByteFormat<0, (outs FSR16:$fsr),
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(ins GPR:$val),
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"movwf ${fsr}L",
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[]>;
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let isTwoAddress = 1 in
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def set_fsrhi:
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ByteFormat<0, (outs FSR16:$dst),
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(ins FSR16:$src, GPR:$val),
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"movwf ${dst}H",
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[]>;
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def copy_fsr:
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Pseudo<(outs FSR16:$dst), (ins FSR16:$src), "copy_fsr $dst, $src", []>;
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//--------------------------
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// Store to memory
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//-------------------------
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// Direct store.
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def movwf :
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ByteFormat<0, (outs),
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(ins GPR:$val, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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"movwf ${ptrlo} + ${offset}",
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[(PIC16Store GPR:$val, tglobaladdr:$ptrlo, (i8 imm:$ptrhi),
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(i8 imm:$offset))]>;
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def movwf_1 :
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ByteFormat<0, (outs),
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(ins GPR:$val, i8mem:$ptrlo, i8imm:$ptrhi, i8imm:$offset),
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"movwf ${ptrlo} + ${offset}",
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[(PIC16Store GPR:$val, texternalsym:$ptrlo, (i8 imm:$ptrhi),
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(i8 imm:$offset))]>;
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// Indirect store. Matched via a DAG replacement pattern.
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def store_indirect :
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ByteFormat<0, (outs),
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(ins GPR:$val, FSR16:$fsr, i8imm:$offset),
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"movwi $offset[$fsr]",
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[]>;
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//----------------------------
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// Load from memory
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//----------------------------
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// Direct load.
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def movf :
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ByteFormat<0, (outs GPR:$dst),
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(ins i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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"movf ${ptrlo} + ${offset}, W",
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[(set GPR:$dst,
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(PIC16Load tglobaladdr:$ptrlo, (i8 imm:$ptrhi),
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(i8 imm:$offset)))]>;
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def movf_1 :
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ByteFormat<0, (outs GPR:$dst),
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(ins i8mem:$ptrlo, i8imm:$ptrhi, i8imm:$offset),
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"movf ${ptrlo} + ${offset}, W",
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[(set GPR:$dst,
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(PIC16Load texternalsym:$ptrlo, (i8 imm:$ptrhi),
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(i8 imm:$offset)))]>;
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// Indirect load. Matched via a DAG replacement pattern.
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def load_indirect :
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ByteFormat<0, (outs GPR:$dst),
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(ins FSR16:$fsr, i8imm:$offset),
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"moviw $offset[$fsr]",
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[]>;
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//-------------------------
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// Bitwise operations patterns
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//--------------------------
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def OrFW : BinOpFW<0, "iorwf", OR>;
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def XOrFW : BinOpFW<0, "xorwf", XOR>;
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def AndFW : BinOpFW<0, "andwf", AND>;
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def OrWF : BinOpWF<0, "iorwf", OR>;
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def XOrWF : BinOpWF<0, "xorwf", XOR>;
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def AndWF : BinOpWF<0, "andwf", AND>;
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//-------------------------
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// Various add/sub patterns.
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//-------------------------
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// let isTwoAddress = 1 in {
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def addfw_1: BinOpFW<0, "addwf", add>;
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def addfw_2: BinOpFW<0, "addwf", addc>;
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def addfwc: BinOpFW<0, "addwfc", adde>; // With Carry.
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// }
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def addwf_1: BinOpWF<0, "addwf", add>;
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def addwf_2: BinOpWF<0, "addwf", addc>;
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def addwfc: BinOpWF<0, "addwfc", adde>; // With Carry.
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// W -= [F] ; load from F and sub the value from W.
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class SUBFW<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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ByteFormat<OpCode, (outs GPR:$dst),
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(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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!strconcat(OpcStr, " $ptrlo + $offset, W"),
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[(set GPR:$dst, (OpNode (PIC16Load diraddr:$ptrlo,
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(i8 imm:$ptrhi), (i8 imm:$offset)),
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GPR:$src))]>;
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//let isTwoAddress = 1 in {
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def subfw_1: SUBFW<0, "subwf", sub>;
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def subfw_2: SUBFW<0, "subwf", subc>;
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def subfwb: SUBFW<0, "subwfb", sube>; // With Borrow.
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//}
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// [F] -= W ;
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class SUBWF<bits<6> OpCode, string OpcStr, SDNode OpNode>:
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ByteFormat<OpCode, (outs),
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(ins GPR:$src, i8imm:$offset, i8mem:$ptrlo, i8imm:$ptrhi),
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!strconcat(OpcStr, " $ptrlo + $offset"),
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[(PIC16Store (OpNode (PIC16Load diraddr:$ptrlo,
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(i8 imm:$ptrhi), (i8 imm:$offset)),
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GPR:$src), diraddr:$ptrlo,
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(i8 imm:$ptrhi), (i8 imm:$offset))]>;
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def subwf_1: SUBWF<0, "subwf", sub>;
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def subwf_2: SUBWF<0, "subwf", subc>;
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def subwfb: SUBWF<0, "subwfb", sube>; // With Borrow.
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// addlw
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// W += C ; add literal to W. (Without carry). May Produce a carry.
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class ADDLW<bits<6> opcode, string OpcStr, SDNode OpNode> :
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LiteralFormat<opcode, (outs GPR:$dst),
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(ins GPR:$src, i8imm:$literal),
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!strconcat(OpcStr, " $literal"),
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[(set GPR:$dst, (OpNode GPR:$src, (i8 imm:$literal)))]>;
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// let isTwoAddress = 1 in {
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def addlw_1 : ADDLW<0, "addlw", add>;
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def addlw_2 : ADDLW<0, "addlw", addc>;
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def addlwc : ADDLW<0, "addlwc", adde>; // With Carry. (Assembler macro).
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//}
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// sublw
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// W = C - W ; sub W from literal. (Without borrow).
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class SUBLW<bits<6> opcode, SDNode OpNode> :
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LiteralFormat<opcode, (outs GPR:$dst),
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(ins GPR:$src, i8imm:$literal),
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"addlw $literal",
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[(set GPR:$dst, (OpNode (i8 imm:$literal), GPR:$src))]>;
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//let isTwoAddress = 1 in {
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def sublw_1 : SUBLW<0, sub>;
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def sublw_2 : SUBLW<0, subc>;
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//}
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// Banksel.
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let isReMaterializable = 1 in {
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def banksel :
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Pseudo<(outs BSR:$dst),
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(ins i8mem:$ptr),
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"banksel $ptr",
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[(set BSR:$dst, (Banksel tglobaladdr:$ptr))]>;
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}
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// Return insn.
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def Return :
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ControlFormat<0, (outs), (ins), "return", [(ret)]>;
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//===----------------------------------------------------------------------===//
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// PIC16 Replacment Patterns.
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//===----------------------------------------------------------------------===//
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// Identify an indirect store and select insns for it.
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def : Pat<(PIC16Store GPR:$val, (MTLO GPR:$loaddr), (MTHI GPR:$hiaddr),
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imm:$offset),
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(store_indirect GPR:$val,
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(set_fsrhi (set_fsrlo GPR:$loaddr), GPR:$hiaddr),
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imm:$offset)>;
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// Identify an indirect load and select insns for it.
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def : Pat<(PIC16Load (MTLO GPR:$loaddr), (MTHI GPR:$hiaddr),
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imm:$offset),
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(load_indirect (set_fsrhi (set_fsrlo GPR:$loaddr), GPR:$hiaddr),
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imm:$offset)>;
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