llvm-6502/test/CodeGen/AArch64/arm64-redzone.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

19 lines
539 B
LLVM

; RUN: llc < %s -march=arm64 -aarch64-redzone | FileCheck %s
define i32 @foo(i32 %a, i32 %b) nounwind ssp {
; CHECK-LABEL: foo:
; CHECK-NOT: sub sp, sp
; CHECK: ret
%a.addr = alloca i32, align 4
%b.addr = alloca i32, align 4
%x = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
store i32 %b, i32* %b.addr, align 4
%tmp = load i32, i32* %a.addr, align 4
%tmp1 = load i32, i32* %b.addr, align 4
%add = add nsw i32 %tmp, %tmp1
store i32 %add, i32* %x, align 4
%tmp2 = load i32, i32* %x, align 4
ret i32 %tmp2
}