mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
0966a4e370
Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp load balancing pass isn't enabled for Cortex-A72 as it's not profitable to have it enabled for this core. Patch by Ranjeet Singh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228140 91177308-0d34-0410-b5e6-96231b3b80d8
18 lines
509 B
LLVM
18 lines
509 B
LLVM
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
|
|
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
|
|
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s
|
|
|
|
%X = type { i64, i64, i64 }
|
|
declare void @f(%X*)
|
|
define void @t() {
|
|
entry:
|
|
%tmp = alloca %X
|
|
call void @f(%X* %tmp)
|
|
; CHECK: add x0, sp, #8
|
|
; CHECK-NEXT-NOT: mov
|
|
call void @f(%X* %tmp)
|
|
; CHECK: add x0, sp, #8
|
|
; CHECK-NEXT-NOT: mov
|
|
ret void
|
|
}
|