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312babc93f
The rematerialized instruction may require a more constrained register class than the register being spilled. In the test case, the spilled register has been inflated to the DPR register class, but we are rematerializing a load of the ssub_0 sub-register which only exists for DPR_VFP2 registers. The register class is reinflated after spilling, so the conservative choice is only temporary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128610 91177308-0d34-0410-b5e6-96231b3b80d8
62 lines
2.3 KiB
LLVM
62 lines
2.3 KiB
LLVM
; RUN: llc < %s -regalloc=greedy -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s
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;
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; ARM tests that crash or fail with the greedy register allocator.
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target triple = "thumbv7-apple-darwin"
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declare double @exp(double)
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; CHECK remat_subreg
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define void @remat_subreg(float* nocapture %x, i32* %y, i32 %n, i32 %z, float %c, float %lambda, float* nocapture %ret_f, float* nocapture %ret_df) nounwind {
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entry:
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%conv16 = fpext float %lambda to double
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%mul17 = fmul double %conv16, -1.000000e+00
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br i1 undef, label %cond.end.us, label %cond.end
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cond.end.us: ; preds = %entry
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unreachable
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cond.end: ; preds = %cond.end, %entry
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%mul = fmul double undef, 0.000000e+00
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%add = fadd double undef, %mul
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%add46 = fadd double undef, undef
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%add75 = fadd double 0.000000e+00, undef
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br i1 undef, label %for.end, label %cond.end
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for.end: ; preds = %cond.end
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%conv78 = sitofp i32 %z to double
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%conv83 = fpext float %c to double
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%mul84 = fmul double %mul17, %conv83
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%call85 = tail call double @exp(double %mul84) nounwind
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%mul86 = fmul double %conv78, %call85
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%add88 = fadd double 0.000000e+00, %mul86
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; CHECK: blx _exp
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%call100 = tail call double @exp(double %mul84) nounwind
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%mul101 = fmul double undef, %call100
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%add103 = fadd double %add46, %mul101
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%mul111 = fmul double undef, %conv83
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%mul119 = fmul double %mul111, undef
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%add121 = fadd double undef, %mul119
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%div = fdiv double 1.000000e+00, %conv16
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%div126 = fdiv double %add, %add75
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%sub = fsub double %div, %div126
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%div129 = fdiv double %add103, %add88
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%add130 = fadd double %sub, %div129
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%conv131 = fptrunc double %add130 to float
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store float %conv131, float* %ret_f, align 4
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%mul139 = fmul double %div129, %div129
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%div142 = fdiv double %add121, %add88
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%sub143 = fsub double %mul139, %div142
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; %lambda is passed on the stack, and the stack slot load is rematerialized.
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; The rematted load of a float constrains the D register used for the mul.
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; CHECK: vldr
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%mul146 = fmul float %lambda, %lambda
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%conv147 = fpext float %mul146 to double
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%div148 = fdiv double 1.000000e+00, %conv147
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%sub149 = fsub double %sub143, %div148
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%conv150 = fptrunc double %sub149 to float
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store float %conv150, float* %ret_df, align 4
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ret void
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}
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