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https://github.com/c64scene-ar/llvm-6502.git
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a44126f432
Summary: Follow up to [x32] "Use ebp/esp as frame and stack pointer": http://reviews.llvm.org/D4617 In that earlier patch, NaCl64 was made to always use rbp. That's needed for most cases because rbp should hold a full 64-bit address within the NaCl sandbox so that load/stores off of rbp don't require sandbox adjustment (zeroing the top 32-bits, then filling those by adding r15). However, llvm.frameaddress returns a pointer and pointers are 32-bit for NaCl64. In this case, use ebp instead, which will make the register copy type check. A similar mechanism may be needed for llvm.eh.return, but is not added in this change. Test Plan: test/CodeGen/X86/frameaddr.ll Reviewers: dschuff, nadav Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D6514 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223510 91177308-0d34-0410-b5e6-96231b3b80d8
143 lines
5.0 KiB
C++
143 lines
5.0 KiB
C++
//===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
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#define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "X86GenRegisterInfo.inc"
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namespace llvm {
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class Type;
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class TargetInstrInfo;
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class X86Subtarget;
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class X86RegisterInfo final : public X86GenRegisterInfo {
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public:
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const X86Subtarget &Subtarget;
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private:
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/// Is64Bit - Is the target 64-bits.
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///
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bool Is64Bit;
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/// IsWin64 - Is the target on of win64 flavours
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///
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bool IsWin64;
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/// SlotSize - Stack slot size in bytes.
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///
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unsigned SlotSize;
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/// StackPtr - X86 physical register used as stack ptr.
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///
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unsigned StackPtr;
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/// FramePtr - X86 physical register used as frame ptr.
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///
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unsigned FramePtr;
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/// BasePtr - X86 physical register used as a base ptr in complex stack
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/// frames. I.e., when we need a 3rd base, not just SP and FP, due to
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/// variable size stack objects.
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unsigned BasePtr;
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public:
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X86RegisterInfo(const X86Subtarget &STI);
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// FIXME: This should be tablegen'd like getDwarfRegNum is
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int getSEHRegNum(unsigned i) const;
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/// Code Generation virtual methods...
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///
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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/// getMatchingSuperRegClass - Return a subclass of the specified register
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/// class A so that each register in it has a sub-register of the
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/// specified sub-register index which is in the specified register class B.
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const TargetRegisterClass *
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getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B,
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unsigned Idx) const override;
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const TargetRegisterClass *
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getSubClassWithSubReg(const TargetRegisterClass *RC,
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unsigned Idx) const override;
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const TargetRegisterClass*
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getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
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/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
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/// values.
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF,
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unsigned Kind = 0) const override;
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/// getCrossCopyRegClass - Returns a legal register class to copy a register
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/// in the specified class to or from. Returns NULL if it is possible to copy
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/// between a two registers of the specified class.
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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/// getCalleeSavedRegs - Return a null-terminated list of all of the
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/// callee-save registers on this target.
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const MCPhysReg *
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getCalleeSavedRegs(const MachineFunction* MF) const override;
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const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
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const uint32_t *getNoPreservedMask() const;
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses and
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/// should be considered unavailable at all times, e.g. SP, RA. This is used by
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/// register scavenger to determine what registers are free.
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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bool hasBasePointer(const MachineFunction &MF) const;
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bool canRealignStack(const MachineFunction &MF) const;
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bool needsStackRealignment(const MachineFunction &MF) const override;
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bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
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int &FrameIdx) const override;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const;
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unsigned getStackRegister() const { return StackPtr; }
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unsigned getBaseRegister() const { return BasePtr; }
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// FIXME: Move to FrameInfok
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unsigned getSlotSize() const { return SlotSize; }
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};
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// getX86SubSuperRegister - X86 utility function. It returns the sub or super
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// register of a specific X86 register.
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// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX
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unsigned getX86SubSuperRegister(unsigned, MVT::SimpleValueType, bool High=false);
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//get512BitRegister - X86 utility - returns 512-bit super register
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unsigned get512BitSuperRegister(unsigned Reg);
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} // End llvm namespace
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#endif
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