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c4cc40c001
- Add TSFlags for the instruction formats. The idea here is to use as much encoding as possible from getBinaryCodeForInstr, and having TSFLags formats for that would make it easier to encode most part of the instructions (since Mips encodings are pretty straightforward) - Improve the mips mechanism for compilation callback - Add Mips specific code for invalidating the instruction cache - Next patch will address wrong tablegen encoding Commit msg added by my own but the patch is from Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139688 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.3 KiB
C++
42 lines
1.3 KiB
C++
//===- MipsRelocations.h - Mips Code Relocations ---------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===---------------------------------------------------------------------===//
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//
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// This file defines the Mips target-specific relocation types
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// (for relocation-model=static).
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//
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//===---------------------------------------------------------------------===//
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#ifndef MIPSRELOCATIONS_H_
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#define MIPSRELOCATIONS_H_
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#include "llvm/CodeGen/MachineRelocation.h"
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namespace llvm {
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namespace Mips{
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enum RelocationType {
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// reloc_mips_branch - pc relative relocation for branches. The lower 18
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// bits of the difference between the branch target and the branch
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// instruction, shifted right by 2.
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reloc_mips_branch = 1,
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// reloc_mips_hi - upper 16 bits of the address (modified by +1 if the
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// lower 16 bits of the address is negative).
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reloc_mips_hi = 2,
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// reloc_mips_lo - lower 16 bits of the address.
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reloc_mips_lo = 3,
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// reloc_mips_26 - lower 28 bits of the address, shifted right by 2.
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reloc_mips_26 = 4
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};
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}
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}
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#endif /* MIPSRELOCATIONS_H_ */
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