Dan Gohman b1e8cad61e Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation, ... which is represented in codegen as an 'and' operation. This matches them with movz instructions, instead of leaving them to be matched by and instructions with an immediate field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54147 91177308-0d34-0410-b5e6-96231b3b80d8		2008-07-28 22:18:25 +00:00
..
Analysis	Fix a subtle bug when removing instructions from memdep. In very specific	2008-07-28 16:00:58 +00:00
Archive	Fold the useful features of alist and alist_node into ilist, and	2008-07-28 21:51:04 +00:00
AsmParser	Update the generated .cvs files.	2008-07-23 00:54:54 +00:00
Bitcode	Enable first-class aggregates support.	2008-07-23 00:34:11 +00:00
CodeGen	Fold the useful features of alist and alist_node into ilist, and	2008-07-28 21:51:04 +00:00
Debugger
ExecutionEngine
Linker
Support	Fold the useful features of alist and alist_node into ilist, and	2008-07-28 21:51:04 +00:00
System	Create temp. file in current path.	2008-07-24 00:35:38 +00:00
Target	Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation,	2008-07-28 22:18:25 +00:00
Transforms	Don't remove volatile loads. Thanks to Duncan for noticing this one.	2008-07-28 20:52:42 +00:00
VMCore	Fold the useful features of alist and alist_node into ilist, and	2008-07-28 21:51:04 +00:00
Makefile