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https://github.com/c64scene-ar/llvm-6502.git
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614051a1c5
Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137711 91177308-0d34-0410-b5e6-96231b3b80d8
375 lines
15 KiB
TableGen
375 lines
15 KiB
TableGen
//===- MipsInstrFPU.td - Mips FPU Instruction Information --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Mips FPU instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Floating Point Instructions
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// ------------------------
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// * 64bit fp:
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// - 32 64-bit registers (default mode)
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// - 16 even 32-bit registers (32-bit compatible mode) for
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// single and double access.
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// * 32bit fp:
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// - 16 even 32-bit registers - single and double (aliased)
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// - 32 32-bit registers (within single-only mode)
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//===----------------------------------------------------------------------===//
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// Floating Point Compare and Branch
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def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>,
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SDTCisVT<1, OtherVT>]>;
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def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
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SDTCisInt<2>]>;
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def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>]>;
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def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
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SDTCisVT<1, i32>,
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SDTCisSameAs<1, 2>]>;
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def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
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SDTCisVT<1, f64>,
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SDTCisVT<0, i32>]>;
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def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
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def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
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def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
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def MipsFPRound : SDNode<"MipsISD::FPRound", SDTFPRoundOp, [SDNPOptInGlue]>;
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def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
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[SDNPHasChain, SDNPOptInGlue]>;
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def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
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def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
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SDT_MipsExtractElementF64>;
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// Operand for printing out a condition code.
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let PrintMethod = "printFCCOperand" in
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def condcode : Operand<i32>;
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//===----------------------------------------------------------------------===//
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// Feature predicates.
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//===----------------------------------------------------------------------===//
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def In32BitMode : Predicate<"!Subtarget.isFP64bit()">;
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def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
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def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
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def IsNotMipsI : Predicate<"!Subtarget.isMips1()">;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//
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// A set of multiclasses is used to address the register usage.
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//
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// S32 - single precision in 16 32bit even fp registers
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// single precision in 32 32bit fp registers in SingleOnly mode
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// S64 - single precision in 32 64bit fp registers (In64BitMode)
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// D32 - double precision in 16 32bit even fp registers
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// D64 - double precision in 32 64bit fp registers (In64BitMode)
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//
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// Only S32 and D32 are supported right now.
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//===----------------------------------------------------------------------===//
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multiclass FFR1_1<bits<6> funct, string asmstr>
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{
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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!strconcat(asmstr, ".s\t$fd, $fs"), []>;
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def _D32 : FFR<0x11, funct, 0x1, (outs FGR32:$fd), (ins AFGR64:$fs),
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!strconcat(asmstr, ".d\t$fd, $fs"), []>, Requires<[In32BitMode]>;
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}
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multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
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{
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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!strconcat(asmstr, ".s\t$fd, $fs"),
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[(set FGR32:$fd, (FOp FGR32:$fs))]>;
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def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
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!strconcat(asmstr, ".d\t$fd, $fs"),
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[(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>;
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}
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class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
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RegisterClass RcDst, string asmstr>:
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FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
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!strconcat(asmstr, "\t$fd, $fs"), []>;
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multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp, bit isComm = 0> {
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let isCommutable = isComm in {
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def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
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(ins FGR32:$fs, FGR32:$ft),
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!strconcat(asmstr, ".s\t$fd, $fs, $ft"),
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[(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>;
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def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
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(ins AFGR64:$fs, AFGR64:$ft),
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!strconcat(asmstr, ".d\t$fd, $fs, $ft"),
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[(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
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Requires<[In32BitMode]>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Floating Point Instructions
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//===----------------------------------------------------------------------===//
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let ft = 0 in {
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defm FLOOR_W : FFR1_1<0b001111, "floor.w">;
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defm CEIL_W : FFR1_1<0b001110, "ceil.w">;
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defm ROUND_W : FFR1_1<0b001100, "round.w">;
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defm TRUNC_W : FFR1_1<0b001101, "trunc.w">;
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defm CVTW : FFR1_1<0b100100, "cvt.w">;
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defm FABS : FFR1_2<0b000101, "abs", fabs>;
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defm FNEG : FFR1_2<0b000111, "neg", fneg>;
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defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
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/// Convert to Single Precison
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def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">;
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let Predicates = [IsNotSingleFloat] in {
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/// Ceil to long signed integer
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def CEIL_LS : FFR1_3<0b001010, 0x0, FGR32, FGR32, "ceil.l">;
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def CEIL_LD : FFR1_3<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">;
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/// Round to long signed integer
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def ROUND_LS : FFR1_3<0b001000, 0x0, FGR32, FGR32, "round.l">;
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def ROUND_LD : FFR1_3<0b001000, 0x1, AFGR64, AFGR64, "round.l">;
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/// Floor to long signed integer
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def FLOOR_LS : FFR1_3<0b001011, 0x0, FGR32, FGR32, "floor.l">;
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def FLOOR_LD : FFR1_3<0b001011, 0x1, AFGR64, AFGR64, "floor.l">;
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/// Trunc to long signed integer
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def TRUNC_LS : FFR1_3<0b001001, 0x0, FGR32, FGR32, "trunc.l">;
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def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
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/// Convert to long signed integer
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def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
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def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
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/// Convert to Double Precison
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def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
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def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
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def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
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/// Convert to Single Precison
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def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
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def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
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}
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}
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// The odd-numbered registers are only referenced when doing loads,
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// stores, and moves between floating-point and integer registers.
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// When defining instructions, we reference all 32-bit registers,
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// regardless of register aliasing.
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let fd = 0 in {
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/// Move Control Registers From/To CPU Registers
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def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins CCR:$fs),
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"cfc1\t$rt, $fs", []>;
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def CTC1 : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs),
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"ctc1\t$fs, $rt", []>;
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def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
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"mfc1\t$rt, $fs", []>;
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def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
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"mtc1\t$rt, $fs", []>;
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}
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def FMOV_S32 : FFR<0x11, 0b000110, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
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"mov.s\t$fd, $fs", []>;
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def FMOV_D32 : FFR<0x11, 0b000110, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
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"mov.d\t$fd, $fs", []>;
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/// Floating Point Memory Instructions
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let Predicates = [IsNotSingleFloat] in {
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def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
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"ldc1\t$ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
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def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr),
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"sdc1\t$ft, $addr", [(store AFGR64:$ft, addr:$addr)]>;
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}
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// LWC1 and SWC1 can always be emitted with odd registers.
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def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1\t$ft, $addr",
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[(set FGR32:$ft, (load addr:$addr))]>;
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def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr),
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"swc1\t$ft, $addr", [(store FGR32:$ft, addr:$addr)]>;
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/// Floating-point Aritmetic
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defm FADD : FFR1_4<0x10, "add", fadd, 1>;
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defm FDIV : FFR1_4<0x03, "div", fdiv>;
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defm FMUL : FFR1_4<0x02, "mul", fmul, 1>;
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defm FSUB : FFR1_4<0x01, "sub", fsub>;
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//===----------------------------------------------------------------------===//
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// Floating Point Branch Codes
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//===----------------------------------------------------------------------===//
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// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
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// They must be kept in synch.
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def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
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def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
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def MIPS_BRANCH_FL : PatLeaf<(i32 2)>;
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def MIPS_BRANCH_TL : PatLeaf<(i32 3)>;
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/// Floating Point Branch of False/True (Likely)
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let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
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class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (outs),
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(ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
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[(MipsFPBrcond op, bb:$dst)]>;
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def BC1F : FBRANCH<MIPS_BRANCH_F, "bc1f">;
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def BC1T : FBRANCH<MIPS_BRANCH_T, "bc1t">;
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def BC1FL : FBRANCH<MIPS_BRANCH_FL, "bc1fl">;
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def BC1TL : FBRANCH<MIPS_BRANCH_TL, "bc1tl">;
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//===----------------------------------------------------------------------===//
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// Floating Point Flag Conditions
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//===----------------------------------------------------------------------===//
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// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
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// They must be kept in synch.
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def MIPS_FCOND_F : PatLeaf<(i32 0)>;
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def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
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def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>;
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def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
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def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
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def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
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def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
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def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
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def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
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def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
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def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
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def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
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def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
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def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
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def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
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def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
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/// Floating Point Compare
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let hasDelaySlot = 1, Defs=[FCR31] in {
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def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
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"c.$cc.s\t$fs, $ft",
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[(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>;
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def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
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"c.$cc.d\t$fs, $ft",
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[(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>,
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Requires<[In32BitMode]>;
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}
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// Conditional moves:
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// These instructions are expanded in
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// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
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// conditional move instructions.
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// flag:int, data:float
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let usesCustomInserter = 1, Constraints = "$F = $dst" in
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class CondMovIntFP<RegisterClass RC, bits<5> fmt, bits<6> func,
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string instr_asm> :
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FFR<0x11, func, fmt, (outs RC:$dst), (ins RC:$T, CPURegs:$cond, RC:$F),
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!strconcat(instr_asm, "\t$dst, $T, $cond"), []>;
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def MOVZ_S : CondMovIntFP<FGR32, 16, 18, "movz.s">;
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def MOVN_S : CondMovIntFP<FGR32, 16, 19, "movn.s">;
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let Predicates = [In32BitMode] in {
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def MOVZ_D : CondMovIntFP<AFGR64, 17, 18, "movz.d">;
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def MOVN_D : CondMovIntFP<AFGR64, 17, 19, "movn.d">;
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}
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defm : MovzPats<FGR32, MOVZ_S>;
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defm : MovnPats<FGR32, MOVN_S>;
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let Predicates = [In32BitMode] in {
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defm : MovzPats<AFGR64, MOVZ_D>;
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defm : MovnPats<AFGR64, MOVN_D>;
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}
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let usesCustomInserter = 1, Uses = [FCR31], Constraints = "$F = $dst" in {
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// flag:float, data:int
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class CondMovFPInt<SDNode cmov, bits<1> tf, string instr_asm> :
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FCMOV<tf, (outs CPURegs:$dst), (ins CPURegs:$T, CPURegs:$F),
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!strconcat(instr_asm, "\t$dst, $T, $$fcc0"),
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[(set CPURegs:$dst, (cmov CPURegs:$T, CPURegs:$F))]>;
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// flag:float, data:float
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class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
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string instr_asm> :
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FFCMOV<fmt, tf, (outs RC:$dst), (ins RC:$T, RC:$F),
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!strconcat(instr_asm, "\t$dst, $T, $$fcc0"),
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[(set RC:$dst, (cmov RC:$T, RC:$F))]>;
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}
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def MOVT : CondMovFPInt<MipsCMovFP_T, 1, "movt">;
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def MOVF : CondMovFPInt<MipsCMovFP_F, 0, "movf">;
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def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
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def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
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let Predicates = [In32BitMode] in {
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def MOVT_D : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
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def MOVF_D : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
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}
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//===----------------------------------------------------------------------===//
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// Floating Point Pseudo-Instructions
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//===----------------------------------------------------------------------===//
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def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
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"# MOVCCRToCCR", []>;
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// This pseudo instr gets expanded into 2 mtc1 instrs after register
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// allocation.
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def BuildPairF64 :
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MipsPseudo<(outs AFGR64:$dst),
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(ins CPURegs:$lo, CPURegs:$hi), "",
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[(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>;
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// This pseudo instr gets expanded into 2 mfc1 instrs after register
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// allocation.
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// if n is 0, lower part of src is extracted.
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// if n is 1, higher part of src is extracted.
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def ExtractElementF64 :
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MipsPseudo<(outs CPURegs:$dst),
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(ins AFGR64:$src, i32imm:$n), "",
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[(set CPURegs:$dst,
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(MipsExtractElementF64 AFGR64:$src, imm:$n))]>;
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//===----------------------------------------------------------------------===//
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// Floating Point Patterns
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//===----------------------------------------------------------------------===//
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def fpimm0 : PatLeaf<(fpimm), [{
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return N->isExactlyValue(+0.0);
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}]>;
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def fpimm0neg : PatLeaf<(fpimm), [{
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return N->isExactlyValue(-0.0);
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}]>;
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def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
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def : Pat<(f32 fpimm0neg), (FNEG_S32 (MTC1 ZERO))>;
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def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
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def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
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def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>;
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def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
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def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>;
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def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>;
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let Predicates = [In32BitMode] in {
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def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>;
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def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>;
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}
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// MipsFPRound is only emitted for MipsI targets.
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def : Pat<(f32 (MipsFPRound AFGR64:$src)), (CVTW_D32 AFGR64:$src)>;
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