mirror of
https://github.com/c64scene-ar/llvm-6502.git
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23dc769a9b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160270 91177308-0d34-0410-b5e6-96231b3b80d8
322 lines
10 KiB
C++
322 lines
10 KiB
C++
//===-- SICodeEmitter.cpp - SI Code Emitter -------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The SI code emitter produces machine code that can be executed directly on
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// the GPU device.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUUtil.h"
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#include "AMDILCodeEmitter.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Target/TargetMachine.h"
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#include <stdio.h>
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#define LITERAL_REG 255
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#define VGPR_BIT(src_idx) (1ULL << (9 * src_idx - 1))
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using namespace llvm;
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namespace {
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class SICodeEmitter : public MachineFunctionPass, public AMDILCodeEmitter {
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private:
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static char ID;
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formatted_raw_ostream &_OS;
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const TargetMachine *TM;
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void emitState(MachineFunction & MF);
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void emitInstr(MachineInstr &MI);
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void outputBytes(uint64_t value, unsigned bytes);
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unsigned GPRAlign(const MachineInstr &MI, unsigned OpNo, unsigned shift)
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const;
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public:
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SICodeEmitter(formatted_raw_ostream &OS) : MachineFunctionPass(ID),
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_OS(OS), TM(NULL) { }
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const char *getPassName() const { return "SI Code Emitter"; }
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bool runOnMachineFunction(MachineFunction &MF);
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/// getMachineOpValue - Return the encoding for MO
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virtual uint64_t getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const;
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/// GPR4AlignEncode - Encoding for when 4 consectuive registers are used
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virtual unsigned GPR4AlignEncode(const MachineInstr &MI, unsigned OpNo)
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const;
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/// GPR2AlignEncode - Encoding for when 2 consecutive registers are used
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virtual unsigned GPR2AlignEncode(const MachineInstr &MI, unsigned OpNo)
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const;
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/// i32LiteralEncode - Encode an i32 literal this is used as an operand
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/// for an instruction in place of a register.
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virtual uint64_t i32LiteralEncode(const MachineInstr &MI, unsigned OpNo)
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const;
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/// SMRDmemriEncode - Encoding for SMRD indexed loads
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virtual uint32_t SMRDmemriEncode(const MachineInstr &MI, unsigned OpNo)
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const;
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/// VOPPostEncode - Post-Encoder method for VOP instructions
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virtual uint64_t VOPPostEncode(const MachineInstr &MI,
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uint64_t Value) const;
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};
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}
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char SICodeEmitter::ID = 0;
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FunctionPass *llvm::createSICodeEmitterPass(formatted_raw_ostream &OS) {
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return new SICodeEmitter(OS);
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}
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void SICodeEmitter::emitState(MachineFunction & MF)
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{
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unsigned maxSGPR = 0;
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unsigned maxVGPR = 0;
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bool VCCUsed = false;
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const SIRegisterInfo * RI =
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static_cast<const SIRegisterInfo*>(TM->getRegisterInfo());
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SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>();
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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unsigned numOperands = MI.getNumOperands();
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for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
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MachineOperand & MO = MI.getOperand(op_idx);
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unsigned maxUsed;
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unsigned width = 0;
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bool isSGPR = false;
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unsigned reg;
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unsigned hwReg;
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if (!MO.isReg()) {
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continue;
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}
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reg = MO.getReg();
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if (reg == AMDGPU::VCC) {
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VCCUsed = true;
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continue;
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}
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if (AMDGPU::SReg_32RegClass.contains(reg)) {
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isSGPR = true;
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width = 1;
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} else if (AMDGPU::VReg_32RegClass.contains(reg)) {
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isSGPR = false;
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width = 1;
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} else if (AMDGPU::SReg_64RegClass.contains(reg)) {
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isSGPR = true;
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width = 2;
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} else if (AMDGPU::VReg_64RegClass.contains(reg)) {
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isSGPR = false;
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width = 2;
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} else if (AMDGPU::SReg_128RegClass.contains(reg)) {
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isSGPR = true;
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width = 4;
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} else if (AMDGPU::VReg_128RegClass.contains(reg)) {
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isSGPR = false;
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width = 4;
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} else if (AMDGPU::SReg_256RegClass.contains(reg)) {
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isSGPR = true;
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width = 8;
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} else {
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assert("!Unknown register class");
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}
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hwReg = RI->getEncodingValue(reg);
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maxUsed = ((hwReg + 1) * width) - 1;
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if (isSGPR) {
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maxSGPR = maxUsed > maxSGPR ? maxUsed : maxSGPR;
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} else {
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maxVGPR = maxUsed > maxVGPR ? maxUsed : maxVGPR;
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}
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}
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}
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}
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if (VCCUsed) {
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maxSGPR += 2;
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}
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outputBytes(maxSGPR + 1, 4);
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outputBytes(maxVGPR + 1, 4);
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outputBytes(MFI->spi_ps_input_addr, 4);
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}
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bool SICodeEmitter::runOnMachineFunction(MachineFunction &MF)
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{
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TM = &MF.getTarget();
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const AMDILSubtarget &STM = TM->getSubtarget<AMDILSubtarget>();
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if (STM.dumpCode()) {
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MF.dump();
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}
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emitState(MF);
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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if (MI.getOpcode() != AMDGPU::KILL && MI.getOpcode() != AMDGPU::RETURN) {
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emitInstr(MI);
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}
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}
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}
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// Emit S_END_PGM
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MachineInstr * End = BuildMI(MF, DebugLoc(),
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TM->getInstrInfo()->get(AMDGPU::S_ENDPGM));
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emitInstr(*End);
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return false;
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}
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void SICodeEmitter::emitInstr(MachineInstr &MI)
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{
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const SIInstrInfo * SII = static_cast<const SIInstrInfo*>(TM->getInstrInfo());
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uint64_t hwInst = getBinaryCodeForInstr(MI);
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if ((hwInst & 0xffffffff) == 0xffffffff) {
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fprintf(stderr, "Unsupported Instruction: \n");
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MI.dump();
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abort();
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}
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unsigned bytes = SII->getEncodingBytes(MI);
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outputBytes(hwInst, bytes);
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}
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uint64_t SICodeEmitter::getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const
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{
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const SIRegisterInfo * RI =
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static_cast<const SIRegisterInfo*>(TM->getRegisterInfo());
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switch(MO.getType()) {
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case MachineOperand::MO_Register:
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return RI->getEncodingValue(MO.getReg());
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case MachineOperand::MO_Immediate:
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return MO.getImm();
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case MachineOperand::MO_FPImmediate:
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// XXX: Not all instructions can use inline literals
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// XXX: We should make sure this is a 32-bit constant
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return LITERAL_REG | (MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue() << 32);
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default:
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llvm_unreachable("Encoding of this operand type is not supported yet.");
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break;
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}
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}
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unsigned SICodeEmitter::GPRAlign(const MachineInstr &MI, unsigned OpNo,
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unsigned shift) const
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{
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const SIRegisterInfo * RI =
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static_cast<const SIRegisterInfo*>(TM->getRegisterInfo());
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unsigned regCode = RI->getEncodingValue(MI.getOperand(OpNo).getReg());
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return regCode >> shift;
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}
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unsigned SICodeEmitter::GPR4AlignEncode(const MachineInstr &MI,
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unsigned OpNo) const
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{
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return GPRAlign(MI, OpNo, 2);
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}
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unsigned SICodeEmitter::GPR2AlignEncode(const MachineInstr &MI,
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unsigned OpNo) const
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{
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return GPRAlign(MI, OpNo, 1);
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}
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uint64_t SICodeEmitter::i32LiteralEncode(const MachineInstr &MI,
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unsigned OpNo) const
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{
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return LITERAL_REG | (MI.getOperand(OpNo).getImm() << 32);
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}
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#define SMRD_OFFSET_MASK 0xff
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#define SMRD_IMM_SHIFT 8
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#define SMRD_SBASE_MASK 0x3f
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#define SMRD_SBASE_SHIFT 9
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/// SMRDmemriEncode - This function is responsibe for encoding the offset
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/// and the base ptr for SMRD instructions it should return a bit string in
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/// this format:
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///
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/// OFFSET = bits{7-0}
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/// IMM = bits{8}
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/// SBASE = bits{14-9}
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///
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uint32_t SICodeEmitter::SMRDmemriEncode(const MachineInstr &MI,
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unsigned OpNo) const
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{
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uint32_t encoding;
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const MachineOperand &OffsetOp = MI.getOperand(OpNo + 1);
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//XXX: Use this function for SMRD loads with register offsets
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assert(OffsetOp.isImm());
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encoding =
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(getMachineOpValue(MI, OffsetOp) & SMRD_OFFSET_MASK)
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| (1 << SMRD_IMM_SHIFT) //XXX If the Offset is a register we shouldn't set this bit
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| ((GPR2AlignEncode(MI, OpNo) & SMRD_SBASE_MASK) << SMRD_SBASE_SHIFT)
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;
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return encoding;
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}
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/// Set the "VGPR" bit for VOP args that can take either a VGPR or a SGPR.
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/// XXX: It would be nice if we could handle this without a PostEncode function.
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uint64_t SICodeEmitter::VOPPostEncode(const MachineInstr &MI,
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uint64_t Value) const
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{
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const SIInstrInfo * SII = static_cast<const SIInstrInfo*>(TM->getInstrInfo());
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unsigned encodingType = SII->getEncodingType(MI);
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unsigned numSrcOps;
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unsigned vgprBitOffset;
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if (encodingType == SIInstrEncodingType::VOP3) {
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numSrcOps = 3;
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vgprBitOffset = 32;
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} else {
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numSrcOps = 1;
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vgprBitOffset = 0;
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}
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// Add one to skip over the destination reg operand.
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for (unsigned opIdx = 1; opIdx < numSrcOps + 1; opIdx++) {
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if (!MI.getOperand(opIdx).isReg()) {
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continue;
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}
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unsigned reg = MI.getOperand(opIdx).getReg();
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if (AMDGPU::VReg_32RegClass.contains(reg)
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|| AMDGPU::VReg_64RegClass.contains(reg)) {
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Value |= (VGPR_BIT(opIdx)) << vgprBitOffset;
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}
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}
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return Value;
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}
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void SICodeEmitter::outputBytes(uint64_t value, unsigned bytes)
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{
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for (unsigned i = 0; i < bytes; i++) {
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_OS.write((uint8_t) ((value >> (8 * i)) & 0xff));
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}
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}
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