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https://github.com/c64scene-ar/llvm-6502.git
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3f0dbab963
X86. Basically, this is a reapplication of r158087 with a few fixes. Specifically, (1) the stack pointer is restored from the base pointer before popping callee-saved registers and (2) in obscure cases (see comments in patch) we must cache the value of the original stack adjustment in the prologue and apply it in the epilogue. rdar://11496434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160002 91177308-0d34-0410-b5e6-96231b3b80d8
150 lines
5.2 KiB
C++
150 lines
5.2 KiB
C++
//===-- X86RegisterInfo.h - X86 Register Information Impl -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86REGISTERINFO_H
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#define X86REGISTERINFO_H
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "X86GenRegisterInfo.inc"
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namespace llvm {
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class Type;
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class TargetInstrInfo;
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class X86TargetMachine;
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class X86RegisterInfo : public X86GenRegisterInfo {
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public:
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X86TargetMachine &TM;
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const TargetInstrInfo &TII;
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private:
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/// Is64Bit - Is the target 64-bits.
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///
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bool Is64Bit;
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/// IsWin64 - Is the target on of win64 flavours
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///
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bool IsWin64;
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/// SlotSize - Stack slot size in bytes.
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///
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unsigned SlotSize;
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/// StackPtr - X86 physical register used as stack ptr.
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///
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unsigned StackPtr;
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/// FramePtr - X86 physical register used as frame ptr.
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///
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unsigned FramePtr;
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/// BasePtr - X86 physical register used as a base ptr in complex stack
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/// frames. I.e., when we need a 3rd base, not just SP and FP, due to
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/// variable size stack objects.
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unsigned BasePtr;
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public:
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X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii);
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/// getX86RegNum - Returns the native X86 register number for the given LLVM
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/// register identifier.
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static unsigned getX86RegNum(unsigned RegNo);
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// FIXME: This should be tablegen'd like getDwarfRegNum is
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int getSEHRegNum(unsigned i) const;
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/// getCompactUnwindRegNum - This function maps the register to the number for
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/// compact unwind encoding. Return -1 if the register isn't valid.
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int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const;
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/// Code Generation virtual methods...
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///
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virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
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/// getMatchingSuperRegClass - Return a subclass of the specified register
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/// class A so that each register in it has a sub-register of the
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/// specified sub-register index which is in the specified register class B.
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virtual const TargetRegisterClass *
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getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B, unsigned Idx) const;
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virtual const TargetRegisterClass *
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getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const;
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const TargetRegisterClass*
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getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
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/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
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/// values.
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
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/// getCrossCopyRegClass - Returns a legal register class to copy a register
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/// in the specified class to or from. Returns NULL if it is possible to copy
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/// between a two registers of the specified class.
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const;
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/// getCalleeSavedRegs - Return a null-terminated list of all of the
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/// callee-save registers on this target.
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const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
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const uint32_t *getCallPreservedMask(CallingConv::ID) const;
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/// getReservedRegs - Returns a bitset indexed by physical register number
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/// indicating if a register is a special register that has particular uses and
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/// should be considered unavailable at all times, e.g. SP, RA. This is used by
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/// register scavenger to determine what registers are free.
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BitVector getReservedRegs(const MachineFunction &MF) const;
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bool hasBasePointer(const MachineFunction &MF) const;
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bool canRealignStack(const MachineFunction &MF) const;
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bool needsStackRealignment(const MachineFunction &MF) const;
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bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
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int &FrameIdx) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, RegScavenger *RS = NULL) const;
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// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const;
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unsigned getStackRegister() const { return StackPtr; }
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unsigned getBaseRegister() const { return BasePtr; }
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// FIXME: Move to FrameInfok
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unsigned getSlotSize() const { return SlotSize; }
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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};
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// getX86SubSuperRegister - X86 utility function. It returns the sub or super
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// register of a specific X86 register.
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// e.g. getX86SubSuperRegister(X86::EAX, EVT::i16) return X86:AX
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unsigned getX86SubSuperRegister(unsigned, EVT, bool High=false);
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} // End llvm namespace
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#endif
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