mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
e3e5fcab94
This is a 1-line patch (with a TODO for AVX because that will affect even more regression tests) that lets us substitute the appropriate 64-bit store for the float/double/int domains. It's not clear to me exactly what the difference is between the 0xD6 (MOVPQI2QImr) and 0x7E (MOVSDto64mr) opcodes, but this is apparently the right choice. Differential Revision: http://reviews.llvm.org/D8691 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235014 91177308-0d34-0410-b5e6-96231b3b80d8
79 lines
3.0 KiB
LLVM
79 lines
3.0 KiB
LLVM
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
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; RUN: llc < %s -march=x86 -mattr=+sse4.2 -x86-experimental-vector-widening-legalization | FileCheck %s --check-prefix=CHECK-WIDE
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define void @update(i64* %dst_i, i64* %src_i, i32 %n) nounwind {
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; CHECK-LABEL: update:
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; CHECK-WIDE-LABEL: update:
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entry:
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%dst_i.addr = alloca i64* ; <i64**> [#uses=2]
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%src_i.addr = alloca i64* ; <i64**> [#uses=2]
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%n.addr = alloca i32 ; <i32*> [#uses=2]
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%i = alloca i32, align 4 ; <i32*> [#uses=8]
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%dst = alloca <8 x i8>*, align 4 ; <<8 x i8>**> [#uses=2]
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%src = alloca <8 x i8>*, align 4 ; <<8 x i8>**> [#uses=2]
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store i64* %dst_i, i64** %dst_i.addr
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store i64* %src_i, i64** %src_i.addr
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store i32 %n, i32* %n.addr
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store i32 0, i32* %i
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br label %forcond
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forcond: ; preds = %forinc, %entry
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%tmp = load i32, i32* %i ; <i32> [#uses=1]
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%tmp1 = load i32, i32* %n.addr ; <i32> [#uses=1]
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%cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
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br i1 %cmp, label %forbody, label %afterfor
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forbody: ; preds = %forcond
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%tmp2 = load i32, i32* %i ; <i32> [#uses=1]
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%tmp3 = load i64*, i64** %dst_i.addr ; <i64*> [#uses=1]
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%arrayidx = getelementptr i64, i64* %tmp3, i32 %tmp2 ; <i64*> [#uses=1]
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%conv = bitcast i64* %arrayidx to <8 x i8>* ; <<8 x i8>*> [#uses=1]
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store <8 x i8>* %conv, <8 x i8>** %dst
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%tmp4 = load i32, i32* %i ; <i32> [#uses=1]
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%tmp5 = load i64*, i64** %src_i.addr ; <i64*> [#uses=1]
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%arrayidx6 = getelementptr i64, i64* %tmp5, i32 %tmp4 ; <i64*> [#uses=1]
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%conv7 = bitcast i64* %arrayidx6 to <8 x i8>* ; <<8 x i8>*> [#uses=1]
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store <8 x i8>* %conv7, <8 x i8>** %src
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%tmp8 = load i32, i32* %i ; <i32> [#uses=1]
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%tmp9 = load <8 x i8>*, <8 x i8>** %dst ; <<8 x i8>*> [#uses=1]
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%arrayidx10 = getelementptr <8 x i8>, <8 x i8>* %tmp9, i32 %tmp8 ; <<8 x i8>*> [#uses=1]
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%tmp11 = load i32, i32* %i ; <i32> [#uses=1]
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%tmp12 = load <8 x i8>*, <8 x i8>** %src ; <<8 x i8>*> [#uses=1]
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%arrayidx13 = getelementptr <8 x i8>, <8 x i8>* %tmp12, i32 %tmp11 ; <<8 x i8>*> [#uses=1]
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%tmp14 = load <8 x i8>, <8 x i8>* %arrayidx13 ; <<8 x i8>> [#uses=1]
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%add = add <8 x i8> %tmp14, < i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1 > ; <<8 x i8>> [#uses=1]
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%shr = ashr <8 x i8> %add, < i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2 > ; <<8 x i8>> [#uses=1]
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store <8 x i8> %shr, <8 x i8>* %arrayidx10
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br label %forinc
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; CHECK: %forbody
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; CHECK: pmovzxbw
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; CHECK-NEXT: paddw
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; CHECK-NEXT: psllw $8
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; CHECK-NEXT: psraw $8
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; CHECK-NEXT: psraw $2
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; CHECK-NEXT: pshufb
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; CHECK-NEXT: movq
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;
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; FIXME: We shouldn't require both a movd and an insert.
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; CHECK-WIDE: %forbody
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; CHECK-WIDE: movd
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; CHECK-WIDE-NEXT: pinsrd
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; CHECK-WIDE-NEXT: paddb
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; CHECK-WIDE-NEXT: psrlw $2
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; CHECK-WIDE-NEXT: pand
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; CHECK-WIDE-NEXT: pxor
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; CHECK-WIDE-NEXT: psubb
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; CHECK-WIDE-NEXT: pextrd
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; CHECK-WIDE-NEXT: movd
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forinc: ; preds = %forbody
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%tmp15 = load i32, i32* %i ; <i32> [#uses=1]
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%inc = add i32 %tmp15, 1 ; <i32> [#uses=1]
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store i32 %inc, i32* %i
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br label %forcond
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afterfor: ; preds = %forcond
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ret void
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}
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