llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-03 00:33:09 +00:00

History

Peter Collingbourne b28abbf98b ARM: Only enforce 4-byte alignment on Thumb-2 functions with constant pools.

This appears to have been introduced back in r76698 as part of an unrelated
change. I can find no official ARM documentation stating that Thumb-2 functions
require 4-byte alignment; in fact, ARM documentation appears to contradict
this (see, e.g., ARM Architecture Reference Manual Thumb-2 Supplement,
section 2.6.1: "Thumb-2 enforces 16-bit alignment on all instructions.").

Also remove code that sets alignment for ARM functions, which is redundant
with code in the MachineFunction constructor, and remove the hidden
-arm-align-constant-islands flag, which has been enabled by default since
r146739 (Dec 2011) and has probably received sufficient testing by now.

Differential Revision: http://reviews.llvm.org/D9138

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235636 91177308-0d34-0410-b5e6-96231b3b80d8

2015-04-23 20:31:22 +00:00

AArch64

[AArch64] Add nvcast patterns for v4f16 and v8f16

2015-04-23 17:32:25 +00:00

ARM

ARM: Only enforce 4-byte alignment on Thumb-2 functions with constant pools.

2015-04-23 20:31:22 +00:00

BPF

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