Alexey Volkov 1bd30dce7b [X86] Limit maximum nop length on Silvermont ... Silvermont can only decode one instruction per cycle if the instruction exceeds 8 bytes. Also in Silvermont instructions with more than 3 prefixes will cause 3 cycle penalty. Maximum nop length is limited to 7 bytes when used for padding on Silvermont. For other x86 processors max nop length remains unchanged 15 bytes. Differential Revision: http://reviews.llvm.org/D4374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212321 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-04 07:14:56 +00:00
..
AArch64	aarch64: support target-specific .req assembler directive	2014-07-02 04:50:23 +00:00
ARM	ARM: take care not to set the ThumbFunc bit on TLS data symbols	2014-06-30 09:37:24 +00:00
AsmParser	Allow using .cfi_startproc without a leading symbol.	2014-06-23 15:34:32 +00:00
COFF	Fix .seh_stackalloc 0	2014-07-01 00:42:47 +00:00
Disassembler	[Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields	2014-06-24 01:42:32 +00:00
ELF	Avoid revocations when possible.	2014-07-01 14:34:30 +00:00
MachO	Change the default input for llvm-nm to be a.out instead of standard input	2014-06-23 20:27:53 +00:00
Markup
Mips	[mips] Added support for assembling sdbbp.	2014-06-24 13:00:32 +00:00
PowerPC	Emit DWARF3 call frame information when DWARF3+ debug info is requested	2014-06-19 15:39:33 +00:00
Sparc
SystemZ
X86	[X86] Limit maximum nop length on Silvermont	2014-07-04 07:14:56 +00:00