mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-12 03:32:10 +00:00
5c8b83eb7a
The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212119 91177308-0d34-0410-b5e6-96231b3b80d8
316 lines
8.8 KiB
LLVM
316 lines
8.8 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s
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@var = global i128 0
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define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) {
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; CHECK-LABEL: val_compare_and_swap:
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; CHECK: movq %rsi, %rax
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; CHECK: movq %rcx, %rbx
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; CHECK: movq %r8, %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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%pair = cmpxchg i128* %p, i128 %oldval, i128 %newval acquire acquire
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%val = extractvalue { i128, i1 } %pair, 0
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ret i128 %val
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}
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define void @fetch_and_nand(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_nand:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: movq %rdx, %rcx
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; CHECK: andq [[INCHI]], %rcx
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; CHECK: movq %rax, %rbx
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; INCLO equivalent comes in in %rsi, so it makes sense it stays there.
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; CHECK: andq %rsi, %rbx
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; CHECK: notq %rbx
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; CHECK: notq %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw nand i128* %p, i128 %bits release
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_or(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_or:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: movq %rax, %rbx
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; INCLO equivalent comes in in %rsi, so it makes sense it stays there.
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; CHECK: orq %rsi, %rbx
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; CHECK: movq %rdx, %rcx
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; CHECK: orq [[INCHI]], %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw or i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_add(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_add:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: movq %rax, %rbx
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; INCLO equivalent comes in in %rsi, so it makes sense it stays there.
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; CHECK: addq %rsi, %rbx
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; CHECK: movq %rdx, %rcx
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; CHECK: adcq [[INCHI]], %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw add i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_sub(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_sub:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: movq %rax, %rbx
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; INCLO equivalent comes in in %rsi, so it makes sense it stays there.
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; CHECK: subq %rsi, %rbx
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; CHECK: movq %rdx, %rcx
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; CHECK: sbbq [[INCHI]], %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw sub i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_min(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_min:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: cmpq %rsi, %rax
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; CHECK: setbe [[CMP:%[a-z0-9]+]]
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; CHECK: cmpq [[INCHI]], %rdx
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; CHECK: setle [[HICMP:%[a-z0-9]+]]
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; CHECK: je [[USE_LO:.?LBB[0-9]+_[0-9]+]]
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; CHECK: movb [[HICMP]], [[CMP]]
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; CHECK: [[USE_LO]]:
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; CHECK: testb [[CMP]], [[CMP]]
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; CHECK: movq %rsi, %rbx
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; CHECK: cmovneq %rax, %rbx
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; CHECK: movq [[INCHI]], %rcx
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; CHECK: cmovneq %rdx, %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw min i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_max(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_max:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: cmpq %rsi, %rax
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; CHECK: setae [[CMP:%[a-z0-9]+]]
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; CHECK: cmpq [[INCHI]], %rdx
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; CHECK: setge [[HICMP:%[a-z0-9]+]]
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; CHECK: je [[USE_LO:.?LBB[0-9]+_[0-9]+]]
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; CHECK: movb [[HICMP]], [[CMP]]
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; CHECK: [[USE_LO]]:
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; CHECK: testb [[CMP]], [[CMP]]
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; CHECK: movq %rsi, %rbx
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; CHECK: cmovneq %rax, %rbx
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; CHECK: movq [[INCHI]], %rcx
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; CHECK: cmovneq %rdx, %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw max i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_umin(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_umin:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: cmpq %rsi, %rax
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; CHECK: setbe [[CMP:%[a-z0-9]+]]
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; CHECK: cmpq [[INCHI]], %rdx
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; CHECK: setbe [[HICMP:%[a-z0-9]+]]
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; CHECK: je [[USE_LO:.?LBB[0-9]+_[0-9]+]]
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; CHECK: movb [[HICMP]], [[CMP]]
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; CHECK: [[USE_LO]]:
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; CHECK: testb [[CMP]], [[CMP]]
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; CHECK: movq %rsi, %rbx
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; CHECK: cmovneq %rax, %rbx
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; CHECK: movq [[INCHI]], %rcx
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; CHECK: cmovneq %rdx, %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw umin i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define void @fetch_and_umax(i128* %p, i128 %bits) {
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; CHECK-LABEL: fetch_and_umax:
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; CHECK-DAG: movq %rdx, [[INCHI:%[a-z0-9]+]]
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; CHECK-DAG: movq (%rdi), %rax
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; CHECK-DAG: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: cmpq %rax, %rsi
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; CHECK: setb [[CMP:%[a-z0-9]+]]
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; CHECK: cmpq [[INCHI]], %rdx
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; CHECK: seta [[HICMP:%[a-z0-9]+]]
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; CHECK: je [[USE_LO:.?LBB[0-9]+_[0-9]+]]
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; CHECK: movb [[HICMP]], [[CMP]]
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; CHECK: [[USE_LO]]:
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; CHECK: testb [[CMP]], [[CMP]]
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; CHECK: movq %rsi, %rbx
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; CHECK: cmovneq %rax, %rbx
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; CHECK: movq [[INCHI]], %rcx
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; CHECK: cmovneq %rdx, %rcx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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; CHECK: movq %rax, _var
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; CHECK: movq %rdx, _var+8
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%val = atomicrmw umax i128* %p, i128 %bits seq_cst
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store i128 %val, i128* @var, align 16
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ret void
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}
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define i128 @atomic_load_seq_cst(i128* %p) {
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; CHECK-LABEL: atomic_load_seq_cst:
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; CHECK: xorl %eax, %eax
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; CHECK: xorl %edx, %edx
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; CHECK: xorl %ebx, %ebx
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; CHECK: xorl %ecx, %ecx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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%r = load atomic i128* %p seq_cst, align 16
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ret i128 %r
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}
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define i128 @atomic_load_relaxed(i128* %p) {
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; CHECK: atomic_load_relaxed:
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; CHECK: xorl %eax, %eax
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; CHECK: xorl %edx, %edx
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; CHECK: xorl %ebx, %ebx
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; CHECK: xorl %ecx, %ecx
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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%r = load atomic i128* %p monotonic, align 16
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ret i128 %r
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}
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define void @atomic_store_seq_cst(i128* %p, i128 %in) {
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; CHECK-LABEL: atomic_store_seq_cst:
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; CHECK: movq %rdx, %rcx
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; CHECK: movq %rsi, %rbx
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; CHECK: movq (%rdi), %rax
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; CHECK: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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store atomic i128 %in, i128* %p seq_cst, align 16
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ret void
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}
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define void @atomic_store_release(i128* %p, i128 %in) {
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; CHECK-LABEL: atomic_store_release:
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; CHECK: movq %rdx, %rcx
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; CHECK: movq %rsi, %rbx
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; CHECK: movq (%rdi), %rax
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; CHECK: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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store atomic i128 %in, i128* %p release, align 16
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ret void
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}
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define void @atomic_store_relaxed(i128* %p, i128 %in) {
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; CHECK-LABEL: atomic_store_relaxed:
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; CHECK: movq %rdx, %rcx
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; CHECK: movq %rsi, %rbx
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; CHECK: movq (%rdi), %rax
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; CHECK: movq 8(%rdi), %rdx
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; CHECK: [[LOOP:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: lock
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; CHECK: cmpxchg16b (%rdi)
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; CHECK: jne [[LOOP]]
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store atomic i128 %in, i128* %p unordered, align 16
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ret void
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}
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