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Apparently, the style needs to be agreed upon first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240390 91177308-0d34-0410-b5e6-96231b3b80d8
184 lines
7.0 KiB
C++
184 lines
7.0 KiB
C++
//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the subtarget options of a Target machine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
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#define LLVM_TARGET_TARGETSUBTARGETINFO_H
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#include "llvm/CodeGen/PBQPRAConstraint.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/CodeGen.h"
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namespace llvm {
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class DataLayout;
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class MachineFunction;
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class MachineInstr;
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class SDep;
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class SUnit;
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class TargetFrameLowering;
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class TargetInstrInfo;
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class TargetLowering;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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class TargetSchedModel;
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class TargetSelectionDAGInfo;
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struct MachineSchedPolicy;
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template <typename T> class SmallVectorImpl;
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//===----------------------------------------------------------------------===//
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///
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/// TargetSubtargetInfo - Generic base class for all target subtargets. All
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/// Target-specific options that control code generation and printing should
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/// be exposed through a TargetSubtargetInfo-derived class.
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///
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class TargetSubtargetInfo : public MCSubtargetInfo {
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TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
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void operator=(const TargetSubtargetInfo &) = delete;
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protected: // Can only create subclasses...
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TargetSubtargetInfo();
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public:
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// AntiDepBreakMode - Type of anti-dependence breaking that should
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// be performed before post-RA scheduling.
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typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
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typedef SmallVectorImpl<const TargetRegisterClass *> RegClassVector;
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virtual ~TargetSubtargetInfo();
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// Interfaces to the major aspects of target machine information:
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//
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// -- Instruction opcode and operand information
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// -- Pipelines and scheduling information
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// -- Stack frame information
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// -- Selection DAG lowering information
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//
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// N.B. These objects may change during compilation. It's not safe to cache
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// them between functions.
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virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
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virtual const TargetFrameLowering *getFrameLowering() const {
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return nullptr;
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}
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virtual const TargetLowering *getTargetLowering() const { return nullptr; }
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virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const {
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return nullptr;
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}
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/// getRegisterInfo - If register information is available, return it. If
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/// not, return null. This is kept separate from RegInfo until RegInfo has
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/// details of graph coloring register allocation removed from it.
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///
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virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
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/// getInstrItineraryData - Returns instruction itinerary data for the target
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/// or specific subtarget.
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///
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virtual const InstrItineraryData *getInstrItineraryData() const {
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return nullptr;
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}
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/// Resolve a SchedClass at runtime, where SchedClass identifies an
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/// MCSchedClassDesc with the isVariant property. This may return the ID of
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/// another variant SchedClass, but repeated invocation must quickly terminate
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/// in a nonvariant SchedClass.
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virtual unsigned resolveSchedClass(unsigned SchedClass,
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const MachineInstr *MI,
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const TargetSchedModel *SchedModel) const {
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return 0;
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}
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/// \brief True if the subtarget should run MachineScheduler after aggressive
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/// coalescing.
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///
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/// This currently replaces the SelectionDAG scheduler with the "source" order
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/// scheduler (though see below for an option to turn this off and use the
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/// TargetLowering preference). It does not yet disable the postRA scheduler.
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virtual bool enableMachineScheduler() const;
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/// \brief True if the machine scheduler should disable the TLI preference
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/// for preRA scheduling with the source level scheduler.
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virtual bool enableMachineSchedDefaultSched() const { return true; }
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/// \brief True if the subtarget should enable joining global copies.
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///
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/// By default this is enabled if the machine scheduler is enabled, but
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/// can be overridden.
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virtual bool enableJoinGlobalCopies() const;
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/// True if the subtarget should run a scheduler after register allocation.
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///
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/// By default this queries the PostRAScheduling bit in the scheduling model
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/// which is the preferred way to influence this.
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virtual bool enablePostRAScheduler() const;
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/// \brief True if the subtarget should run the atomic expansion pass.
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virtual bool enableAtomicExpand() const;
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/// \brief Override generic scheduling policy within a region.
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///
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/// This is a convenient way for targets that don't provide any custom
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/// scheduling heuristics (no custom MachineSchedStrategy) to make
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/// changes to the generic scheduling policy.
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virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
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MachineInstr *begin, MachineInstr *end,
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unsigned NumRegionInstrs) const {}
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// \brief Perform target specific adjustments to the latency of a schedule
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// dependency.
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virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
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// For use with PostRAScheduling: get the anti-dependence breaking that should
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// be performed before post-RA scheduling.
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virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
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// For use with PostRAScheduling: in CriticalPathRCs, return any register
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// classes that should only be considered for anti-dependence breaking if they
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// are on the critical path.
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virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
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return CriticalPathRCs.clear();
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}
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// For use with PostRAScheduling: get the minimum optimization level needed
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// to enable post-RA scheduling.
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virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
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return CodeGenOpt::Default;
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}
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/// \brief True if the subtarget should run the local reassignment
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/// heuristic of the register allocator.
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/// This heuristic may be compile time intensive, \p OptLevel provides
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/// a finer grain to tune the register allocator.
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virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
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/// \brief Enable use of alias analysis during code generation (during MI
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/// scheduling, DAGCombine, etc.).
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virtual bool useAA() const;
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/// \brief Enable the use of the early if conversion pass.
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virtual bool enableEarlyIfConversion() const { return false; }
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/// \brief Return PBQPConstraint(s) for the target.
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///
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/// Override to provide custom PBQP constraints.
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virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
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return nullptr;
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}
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/// Enable tracking of subregister liveness in register allocator.
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virtual bool enableSubRegLiveness() const { return false; }
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};
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} // End llvm namespace
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#endif
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