mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-12 02:33:33 +00:00
68a4ab08b3
This change adds support for immediate and shift-left folding into logical operations. This fixes rdar://problem/18223183. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217118 91177308-0d34-0410-b5e6-96231b3b80d8
139 lines
2.7 KiB
LLVM
139 lines
2.7 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
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; AND
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define i32 @and_rr_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: and_rr_i32
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; CHECK: and w0, w0, w1
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%1 = and i32 %a, %b
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ret i32 %1
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}
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define i64 @and_rr_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: and_rr_i64
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; CHECK: and x0, x0, x1
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%1 = and i64 %a, %b
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ret i64 %1
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}
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define i32 @and_ri_i32(i32 %a) {
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; CHECK-LABEL: and_ri_i32
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; CHECK: and w0, w0, #0xff
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%1 = and i32 %a, 255
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ret i32 %1
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}
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define i64 @and_ri_i64(i64 %a) {
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; CHECK-LABEL: and_ri_i64
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; CHECK: and x0, x0, #0xff
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%1 = and i64 %a, 255
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ret i64 %1
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}
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define i32 @and_rs_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: and_rs_i32
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; CHECK: and w0, w0, w1, lsl #8
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%1 = shl i32 %b, 8
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%2 = and i32 %a, %1
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ret i32 %2
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}
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define i64 @and_rs_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: and_rs_i64
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; CHECK: and x0, x0, x1, lsl #8
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%1 = shl i64 %b, 8
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%2 = and i64 %a, %1
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ret i64 %2
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}
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; OR
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define i32 @or_rr_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: or_rr_i32
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; CHECK: orr w0, w0, w1
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%1 = or i32 %a, %b
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ret i32 %1
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}
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define i64 @or_rr_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: or_rr_i64
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; CHECK: orr x0, x0, x1
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%1 = or i64 %a, %b
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ret i64 %1
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}
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define i32 @or_ri_i32(i32 %a) {
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; CHECK-LABEL: or_ri_i32
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; CHECK: orr w0, w0, #0xff
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%1 = or i32 %a, 255
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ret i32 %1
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}
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define i64 @or_ri_i64(i64 %a) {
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; CHECK-LABEL: or_ri_i64
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; CHECK: orr x0, x0, #0xff
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%1 = or i64 %a, 255
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ret i64 %1
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}
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define i32 @or_rs_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: or_rs_i32
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; CHECK: orr w0, w0, w1, lsl #8
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%1 = shl i32 %b, 8
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%2 = or i32 %a, %1
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ret i32 %2
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}
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define i64 @or_rs_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: or_rs_i64
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; CHECK: orr x0, x0, x1, lsl #8
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%1 = shl i64 %b, 8
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%2 = or i64 %a, %1
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ret i64 %2
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}
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; XOR
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define i32 @xor_rr_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: xor_rr_i32
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; CHECK: eor w0, w0, w1
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%1 = xor i32 %a, %b
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ret i32 %1
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}
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define i64 @xor_rr_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: xor_rr_i64
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; CHECK: eor x0, x0, x1
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%1 = xor i64 %a, %b
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ret i64 %1
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}
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define i32 @xor_ri_i32(i32 %a) {
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; CHECK-LABEL: xor_ri_i32
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; CHECK: eor w0, w0, #0xff
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%1 = xor i32 %a, 255
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ret i32 %1
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}
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define i64 @xor_ri_i64(i64 %a) {
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; CHECK-LABEL: xor_ri_i64
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; CHECK: eor x0, x0, #0xff
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%1 = xor i64 %a, 255
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ret i64 %1
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}
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define i32 @xor_rs_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: xor_rs_i32
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; CHECK: eor w0, w0, w1, lsl #8
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%1 = shl i32 %b, 8
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%2 = xor i32 %a, %1
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ret i32 %2
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}
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define i64 @xor_rs_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: xor_rs_i64
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; CHECK: eor x0, x0, x1, lsl #8
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%1 = shl i64 %b, 8
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%2 = xor i64 %a, %1
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ret i64 %2
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}
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