Chandler Carruth b3364512fc [x86] Fix another miscompile in the new vector shuffle lowering found ... through the new fuzzer. This one is great: bad operator precedence led the modulus to happen at the wrong point. All the asserts didn't fire because there were usually the right values past the end of the 4 element region we were looking at. Probably could have gotten a crash here with ASan + fuzzing, but the correctness tests pinpointed this really nicely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215092 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-07 09:45:02 +00:00
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AArch64	[AArch64] Add a testcase for r214957.	2014-08-06 13:31:32 +00:00
ARM	ARM: do not generate BLX instructions on Cortex-M CPUs.	2014-08-06 11:13:14 +00:00
CPP
Generic
Hexagon	DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.	2014-08-06 00:21:25 +00:00
Inputs
Mips
MSP430
NVPTX
PowerPC	[PowerPC] Swap arguments and adjust shift count for vsldoi on little endian	2014-08-05 20:47:25 +00:00
R600	R600: Cleanup fadd and fsub tests	2014-08-06 20:27:55 +00:00
SPARC
SystemZ
Thumb
Thumb2	ARM: do not generate BLX instructions on Cortex-M CPUs.	2014-08-06 11:13:14 +00:00
X86	[x86] Fix another miscompile in the new vector shuffle lowering found	2014-08-07 09:45:02 +00:00
XCore