Daniel Dunbar b42dad4761 Revert 78892 and 78895, these break generating working executables on ... x86_64-apple-darwin10. --- Reverse-merging r78895 into '.': U test/CodeGen/PowerPC/2008-12-12-EH.ll U lib/Target/DarwinTargetAsmInfo.cpp --- Reverse-merging r78892 into '.': U include/llvm/Target/DarwinTargetAsmInfo.h U lib/Target/X86/X86TargetAsmInfo.cpp U lib/Target/X86/X86TargetAsmInfo.h U lib/Target/ARM/ARMTargetAsmInfo.h U lib/Target/ARM/ARMTargetMachine.cpp U lib/Target/ARM/ARMTargetAsmInfo.cpp U lib/Target/PowerPC/PPCTargetAsmInfo.cpp U lib/Target/PowerPC/PPCTargetAsmInfo.h U lib/Target/PowerPC/PPCTargetMachine.cpp G lib/Target/DarwinTargetAsmInfo.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78919 91177308-0d34-0410-b5e6-96231b3b80d8		2009-08-13 17:03:38 +00:00
..
COFFTargetAsmInfo.h
DarwinTargetAsmInfo.h	Revert 78892 and 78895, these break generating working executables on	2009-08-13 17:03:38 +00:00
SubtargetFeature.h
Target.td	Add 'isCodeGenOnly' bit to Instruction .td records.	2009-08-11 22:17:52 +00:00
TargetAsmInfo.h
TargetAsmParser.h
TargetCallingConv.td
TargetData.h
TargetELFWriterInfo.h
TargetFrameInfo.h
TargetInstrDesc.h
TargetInstrInfo.h
TargetInstrItineraries.h	Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.	2009-08-12 18:31:53 +00:00
TargetIntrinsicInfo.h
TargetJITInfo.h
TargetLowering.h	Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first.	2009-08-12 00:36:31 +00:00
TargetLoweringObjectFile.h	Change MCSectionELF to represent a section semantically instead of	2009-08-13 05:07:35 +00:00
TargetMachine.h	Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple	2009-08-12 07:22:17 +00:00
TargetMachOWriterInfo.h
TargetOptions.h
TargetRegisterInfo.h	Split EVT into MVT and EVT, the former representing _just_ a primitive type, while	2009-08-11 20:47:22 +00:00
TargetRegistry.h	Change TargetAsmInfo to be constructed via TargetRegistry from a Target+Triple	2009-08-12 07:22:17 +00:00
TargetSchedule.td	Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.	2009-08-12 18:31:53 +00:00
TargetSelect.h
TargetSelectionDAG.td	Add a new "SDTCisVec" SDTypeConstraint. This complements the vAny type.	2009-08-12 22:30:59 +00:00
TargetSubtarget.h	Add callback to allow target to adjust latency of schedule dependency edge.	2009-08-13 16:05:04 +00:00