mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-26 05:32:25 +00:00
ae3a0be92e
integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
36 lines
1.3 KiB
LLVM
36 lines
1.3 KiB
LLVM
; PR2094
|
|
; RUN: llvm-as < %s | llc -march=x86-64 | grep movslq
|
|
; RUN: llvm-as < %s | llc -march=x86-64 | grep addps
|
|
; RUN: llvm-as < %s | llc -march=x86-64 | grep paddd
|
|
; RUN: llvm-as < %s | llc -march=x86-64 | not grep movq
|
|
|
|
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
|
|
target triple = "x86_64-apple-darwin8"
|
|
|
|
define i32 @test1(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind {
|
|
%tmp12 = sext i32 %stride to i64 ; <i64> [#uses=1]
|
|
%mrv = call {i32, i8*, i8*} asm sideeffect "$0 $1 $2 $3 $4 $5 $6",
|
|
"=r,=r,=r,r,r,r,r"( i64 %tmp12, i32 %h, i8* %blk1, i8* %blk2 ) nounwind
|
|
%tmp6 = getresult {i32, i8*, i8*} %mrv, 0
|
|
%tmp7 = call i32 asm sideeffect "set $0",
|
|
"=r,~{dirflag},~{fpsr},~{flags}"( ) nounwind
|
|
ret i32 %tmp7
|
|
}
|
|
|
|
define <4 x float> @test2() nounwind {
|
|
%mrv = call {<4 x float>, <4 x float>} asm "set $0, $1", "=x,=x"()
|
|
%a = getresult {<4 x float>, <4 x float>} %mrv, 0
|
|
%b = getresult {<4 x float>, <4 x float>} %mrv, 1
|
|
%c = fadd <4 x float> %a, %b
|
|
ret <4 x float> %c
|
|
}
|
|
|
|
define <4 x i32> @test3() nounwind {
|
|
%mrv = call {<4 x i32>, <4 x i32>} asm "set $0, $1", "=x,=x"()
|
|
%a = getresult {<4 x i32>, <4 x i32>} %mrv, 0
|
|
%b = getresult {<4 x i32>, <4 x i32>} %mrv, 1
|
|
%c = add <4 x i32> %a, %b
|
|
ret <4 x i32> %c
|
|
}
|
|
|