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https://github.com/c64scene-ar/llvm-6502.git
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645c5b94e2
Darwin prologues save their GPRs in two stages: a narrow push of r0-r7 & lr, followed by a wide push of the remaining registers if there are any. AAPCS uses a single push.w instruction. It turns out that, on average, enough registers get pushed that code is smaller in the AAPCS prologue, which is a nice property for M-class programmers. They also have other options available for back-traces, so can hopefully deal with the fact that FP & LR aren't adjacent in memory. rdar://problem/15909583 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209895 91177308-0d34-0410-b5e6-96231b3b80d8
100 lines
2.8 KiB
LLVM
100 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=thumbv7m-none-macho %s -o - -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NON-FAST
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; RUN: llc -mtriple=thumbv7m-none-macho -O0 %s -o - -relocation-model=pic -disable-fp-elim | FileCheck %s
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; RUN: llc -mtriple=thumbv7m-none-macho -filetype=obj %s -o /dev/null
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; Bare-metal should probably "declare" segments just like normal MachO
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; CHECK: __picsymbolstub4
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; CHECK: __StaticInit
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; CHECK: __text
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@var = external global i32
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define i32 @test_litpool() minsize {
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; CHECK-LABEL: test_litpool:
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%val = load i32* @var
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ret i32 %val
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; Lit-pool entries need to produce a "$non_lazy_ptr" version of the symbol.
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; CHECK: LCPI0_0:
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; CHECK-NEXT: .long L_var$non_lazy_ptr-(LPC0_0+4)
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}
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define i32 @test_movw_movt() {
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; CHECK-LABEL: test_movw_movt:
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%val = load i32* @var
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ret i32 %val
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; movw/movt should also address their symbols MachO-style
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; CHECK: movw [[RTMP:r[0-9]+]], :lower16:(L_var$non_lazy_ptr-(LPC1_0+4))
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; CHECK: movt [[RTMP]], :upper16:(L_var$non_lazy_ptr-(LPC1_0+4))
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; CHECK: LPC1_0:
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; CHECK: add [[RTMP]], pc
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}
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declare void @llvm.trap()
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define void @test_trap() {
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; CHECK-LABEL: test_trap:
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; Bare-metal MachO gets compiled on top of normal MachO toolchain which
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; understands trap natively.
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call void @llvm.trap()
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; CHECK: trap
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ret void
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}
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define i32 @test_frame_ptr() {
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; CHECK-LABEL: test_frame_ptr:
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call void @test_trap()
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; Frame pointer is r11.
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; CHECK: mov r11, sp
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ret i32 42
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}
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%big_arr = type [8 x i32]
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define void @test_two_areas(%big_arr* %addr) {
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; CHECK-LABEL: test_two_areas:
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%val = load %big_arr* %addr
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call void @test_trap()
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store %big_arr %val, %big_arr* %addr
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; This goes with the choice of r7 as FP (largely). FP and LR have to be stored
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; consecutively on the stack for the frame record to be valid, which means we
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; need the 2 register-save areas employed by iOS.
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; CHECK-NON-FAST: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
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; ...
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; CHECK-NON-FAST: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
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ret void
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}
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define void @test_tail_call() {
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; CHECK-LABEL: test_tail_call:
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tail call void @test_trap()
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; Tail calls should be available and use Thumb2 branch.
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; CHECK: b.w _test_trap
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ret void
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}
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define float @test_softfloat_calls(float %in) {
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; CHECK-LABEL: test_softfloat_calls:
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%sum = fadd float %in, %in
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; Soft-float calls should be GNU-style rather than RTABI and should not be the
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; *vfp variants used for ARMv6 iOS.
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; CHECK: blx ___addsf3{{$}}
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ret float %sum
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}
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; Even bare-metal PIC needs GOT-like behaviour, in principle. Depends a bit on
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; the use-case of course, but LLVM doesn't know what that is.
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; CHECK: non_lazy_symbol_pointers
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; CHECK: L_var$non_lazy_ptr:
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; CHECK-NEXT: .indirect_symbol _var
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; All MachO objects should have this to give the linker leeway in removing
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; dead code.
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; CHECK: .subsections_via_symbols
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