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8a9df8f92c
This eliminates extra extract instructions when loading an i8 vector to a float vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210666 91177308-0d34-0410-b5e6-96231b3b80d8
43 lines
1.7 KiB
LLVM
43 lines
1.7 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
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declare float @llvm.AMDGPU.cvt.f32.ubyte0(i32) nounwind readnone
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declare float @llvm.AMDGPU.cvt.f32.ubyte1(i32) nounwind readnone
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declare float @llvm.AMDGPU.cvt.f32.ubyte2(i32) nounwind readnone
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declare float @llvm.AMDGPU.cvt.f32.ubyte3(i32) nounwind readnone
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; SI-LABEL: @test_unpack_byte0_to_float:
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; SI: V_CVT_F32_UBYTE0
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define void @test_unpack_byte0_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32 addrspace(1)* %in, align 4
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte0(i32 %val) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @test_unpack_byte1_to_float:
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; SI: V_CVT_F32_UBYTE1
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define void @test_unpack_byte1_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32 addrspace(1)* %in, align 4
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %val) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @test_unpack_byte2_to_float:
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; SI: V_CVT_F32_UBYTE2
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define void @test_unpack_byte2_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32 addrspace(1)* %in, align 4
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte2(i32 %val) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: @test_unpack_byte3_to_float:
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; SI: V_CVT_F32_UBYTE3
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define void @test_unpack_byte3_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%val = load i32 addrspace(1)* %in, align 4
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%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte3(i32 %val) nounwind readnone
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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