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https://github.com/c64scene-ar/llvm-6502.git
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targets that supported multiple memory operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16614 91177308-0d34-0410-b5e6-96231b3b80d8
379 lines
13 KiB
C++
379 lines
13 KiB
C++
//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the VirtRegMap class.
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//
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// It also contains implementations of the the Spiller interface, which, given a
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// virtual register map and a machine function, eliminates all virtual
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// references by replacing them with physical register references - adding spill
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// code as necessary.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "spiller"
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#include "VirtRegMap.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/STLExtras.h"
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using namespace llvm;
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namespace {
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Statistic<> NumSpills("spiller", "Number of register spills");
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Statistic<> NumStores("spiller", "Number of stores added");
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Statistic<> NumLoads ("spiller", "Number of loads added");
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enum SpillerName { simple, local };
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cl::opt<SpillerName>
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SpillerOpt("spiller",
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cl::desc("Spiller to use: (default: simple)"),
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cl::Prefix,
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cl::values(clEnumVal(simple, " simple spiller"),
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clEnumVal(local, " local spiller"),
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clEnumValEnd),
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cl::init(simple));
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}
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//===----------------------------------------------------------------------===//
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// VirtRegMap implementation
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//===----------------------------------------------------------------------===//
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void VirtRegMap::grow() {
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Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
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Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
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}
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int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
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assert(MRegisterInfo::isVirtualRegister(virtReg));
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assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
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int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
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RC->getAlignment());
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Virt2StackSlotMap[virtReg] = frameIndex;
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++NumSpills;
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return frameIndex;
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}
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void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
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assert(MRegisterInfo::isVirtualRegister(virtReg));
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assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
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"attempt to assign stack slot to already spilled register");
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Virt2StackSlotMap[virtReg] = frameIndex;
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}
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void VirtRegMap::virtFolded(unsigned virtReg,
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MachineInstr* oldMI,
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MachineInstr* newMI) {
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// move previous memory references folded to new instruction
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std::vector<MI2VirtMapTy::mapped_type> regs;
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for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(oldMI),
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E = MI2VirtMap.end(); I != E && I->first == oldMI; ) {
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regs.push_back(I->second);
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MI2VirtMap.erase(I++);
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}
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MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(newMI);
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for (unsigned i = 0, e = regs.size(); i != e; ++i)
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MI2VirtMap.insert(IP, std::make_pair(newMI, regs[i]));
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// add new memory reference
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MI2VirtMap.insert(IP, std::make_pair(newMI, virtReg));
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}
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void VirtRegMap::print(std::ostream &OS) const {
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const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
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OS << "********** REGISTER MAP **********\n";
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for (unsigned i = MRegisterInfo::FirstVirtualRegister,
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e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
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if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
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OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
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}
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for (unsigned i = MRegisterInfo::FirstVirtualRegister,
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e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
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if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
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OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
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OS << '\n';
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}
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void VirtRegMap::dump() const { print(std::cerr); }
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//===----------------------------------------------------------------------===//
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// Simple Spiller Implementation
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//===----------------------------------------------------------------------===//
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Spiller::~Spiller() {}
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namespace {
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struct SimpleSpiller : public Spiller {
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bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap &VRM);
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};
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}
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bool SimpleSpiller::runOnMachineFunction(MachineFunction& MF,
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const VirtRegMap& VRM) {
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DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
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DEBUG(std::cerr << "********** Function: "
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<< MF.getFunction()->getName() << '\n');
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const TargetMachine& TM = MF.getTarget();
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const MRegisterInfo& MRI = *TM.getRegisterInfo();
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// LoadedRegs - Keep track of which vregs are loaded, so that we only load
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// each vreg once (in the case where a spilled vreg is used by multiple
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// operands). This is always smaller than the number of operands to the
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// current machine instr, so it should be small.
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std::vector<unsigned> LoadedRegs;
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for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
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MBBI != E; ++MBBI) {
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DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n");
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MachineBasicBlock &MBB = *MBBI;
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for (MachineBasicBlock::iterator MII = MBB.begin(),
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E = MBB.end(); MII != E; ++MII) {
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MachineInstr &MI = *MII;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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MachineOperand &MOP = MI.getOperand(i);
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if (MOP.isRegister() && MOP.getReg() &&
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MRegisterInfo::isVirtualRegister(MOP.getReg())){
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unsigned VirtReg = MOP.getReg();
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unsigned PhysReg = VRM.getPhys(VirtReg);
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if (VRM.hasStackSlot(VirtReg)) {
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int StackSlot = VRM.getStackSlot(VirtReg);
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if (MOP.isUse() &&
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std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
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== LoadedRegs.end()) {
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MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
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LoadedRegs.push_back(VirtReg);
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++NumLoads;
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DEBUG(std::cerr << '\t' << *prior(MII));
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}
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if (MOP.isDef()) {
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MRI.storeRegToStackSlot(MBB, next(MII), PhysReg,
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VRM.getStackSlot(VirtReg));
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++NumStores;
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}
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}
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MI.SetMachineOperandReg(i, PhysReg);
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}
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}
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DEBUG(std::cerr << '\t' << MI);
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LoadedRegs.clear();
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}
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}
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return true;
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}
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//===----------------------------------------------------------------------===//
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// Local Spiller Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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class LocalSpiller : public Spiller {
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typedef std::vector<unsigned> Phys2VirtMap;
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typedef std::vector<bool> PhysFlag;
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typedef DenseMap<MachineInstr*, VirtReg2IndexFunctor> Virt2MI;
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MachineFunction *MF;
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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const MRegisterInfo *MRI;
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const VirtRegMap *VRM;
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Phys2VirtMap p2vMap_;
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PhysFlag dirty_;
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Virt2MI lastDef_;
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public:
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bool runOnMachineFunction(MachineFunction &MF, const VirtRegMap &VRM);
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private:
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void vacateJustPhysReg(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII,
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unsigned PhysReg);
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void vacatePhysReg(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII,
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unsigned PhysReg) {
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vacateJustPhysReg(MBB, MII, PhysReg);
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for (const unsigned* as = MRI->getAliasSet(PhysReg); *as; ++as)
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vacateJustPhysReg(MBB, MII, *as);
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}
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void handleUse(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII,
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unsigned VirtReg,
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unsigned PhysReg) {
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// check if we are replacing a previous mapping
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if (p2vMap_[PhysReg] != VirtReg) {
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vacatePhysReg(MBB, MII, PhysReg);
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p2vMap_[PhysReg] = VirtReg;
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// load if necessary
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if (VRM->hasStackSlot(VirtReg)) {
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MRI->loadRegFromStackSlot(MBB, MII, PhysReg,
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VRM->getStackSlot(VirtReg));
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++NumLoads;
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DEBUG(std::cerr << "added: " << *prior(MII));
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lastDef_[VirtReg] = MII;
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}
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}
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}
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void handleDef(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII,
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unsigned VirtReg,
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unsigned PhysReg) {
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// check if we are replacing a previous mapping
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if (p2vMap_[PhysReg] != VirtReg)
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vacatePhysReg(MBB, MII, PhysReg);
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p2vMap_[PhysReg] = VirtReg;
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dirty_[PhysReg] = true;
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lastDef_[VirtReg] = MII;
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}
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void eliminateVirtRegsInMBB(MachineBasicBlock& MBB);
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};
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}
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bool LocalSpiller::runOnMachineFunction(MachineFunction &mf,
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const VirtRegMap &vrm) {
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MF = &mf;
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TM = &MF->getTarget();
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TII = TM->getInstrInfo();
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MRI = TM->getRegisterInfo();
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VRM = &vrm;
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p2vMap_.assign(MRI->getNumRegs(), 0);
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dirty_.assign(MRI->getNumRegs(), false);
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DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
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DEBUG(std::cerr << "********** Function: "
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<< MF->getFunction()->getName() << '\n');
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for (MachineFunction::iterator MBB = MF->begin(), E = MF->end();
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MBB != E; ++MBB) {
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lastDef_.grow(MF->getSSARegMap()->getLastVirtReg());
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DEBUG(std::cerr << MBB->getBasicBlock()->getName() << ":\n");
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eliminateVirtRegsInMBB(*MBB);
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// clear map, dirty flag and last ref
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p2vMap_.assign(p2vMap_.size(), 0);
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dirty_.assign(dirty_.size(), false);
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lastDef_.clear();
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}
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return true;
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}
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void LocalSpiller::vacateJustPhysReg(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII,
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unsigned PhysReg) {
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unsigned VirtReg = p2vMap_[PhysReg];
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if (dirty_[PhysReg] && VRM->hasStackSlot(VirtReg)) {
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assert(lastDef_[VirtReg] && "virtual register is mapped "
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"to a register and but was not defined!");
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MachineBasicBlock::iterator lastDef = lastDef_[VirtReg];
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MachineBasicBlock::iterator nextLastRef = next(lastDef);
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MRI->storeRegToStackSlot(*lastDef->getParent(),
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nextLastRef,
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PhysReg,
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VRM->getStackSlot(VirtReg));
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++NumStores;
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DEBUG(std::cerr << "added: " << *prior(nextLastRef);
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std::cerr << "after: " << *lastDef);
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lastDef_[VirtReg] = 0;
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}
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p2vMap_[PhysReg] = 0;
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dirty_[PhysReg] = false;
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}
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void LocalSpiller::eliminateVirtRegsInMBB(MachineBasicBlock &MBB) {
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for (MachineBasicBlock::iterator MI = MBB.begin(), E = MBB.end();
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MI != E; ++MI) {
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// if we have references to memory operands make sure
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// we clear all physical registers that may contain
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// the value of the spilled virtual register
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VirtRegMap::MI2VirtMapTy::const_iterator i, e;
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for (tie(i, e) = VRM->getFoldedVirts(MI); i != e; ++i) {
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if (VRM->hasPhys(i->second))
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vacateJustPhysReg(MBB, MI, VRM->getPhys(i->second));
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}
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// rewrite all used operands
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& op = MI->getOperand(i);
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if (op.isRegister() && op.getReg() && op.isUse() &&
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MRegisterInfo::isVirtualRegister(op.getReg())) {
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unsigned VirtReg = op.getReg();
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unsigned PhysReg = VRM->getPhys(VirtReg);
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handleUse(MBB, MI, VirtReg, PhysReg);
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MI->SetMachineOperandReg(i, PhysReg);
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// mark as dirty if this is def&use
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if (op.isDef()) {
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dirty_[PhysReg] = true;
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lastDef_[VirtReg] = MI;
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}
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}
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}
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// spill implicit physical register defs
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const TargetInstrDescriptor& tid = TII->get(MI->getOpcode());
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for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
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vacatePhysReg(MBB, MI, *id);
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// spill explicit physical register defs
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& op = MI->getOperand(i);
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if (op.isRegister() && op.getReg() && !op.isUse() &&
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MRegisterInfo::isPhysicalRegister(op.getReg()))
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vacatePhysReg(MBB, MI, op.getReg());
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}
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// rewrite def operands (def&use was handled with the
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// uses so don't check for those here)
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& op = MI->getOperand(i);
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if (op.isRegister() && op.getReg() && !op.isUse())
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if (MRegisterInfo::isPhysicalRegister(op.getReg()))
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vacatePhysReg(MBB, MI, op.getReg());
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else {
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unsigned PhysReg = VRM->getPhys(op.getReg());
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handleDef(MBB, MI, op.getReg(), PhysReg);
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MI->SetMachineOperandReg(i, PhysReg);
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}
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}
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DEBUG(std::cerr << '\t' << *MI);
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}
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for (unsigned i = 1, e = p2vMap_.size(); i != e; ++i)
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vacateJustPhysReg(MBB, MBB.getFirstTerminator(), i);
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}
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llvm::Spiller* llvm::createSpiller() {
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switch (SpillerOpt) {
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default: assert(0 && "Unreachable!");
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case local:
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return new LocalSpiller();
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case simple:
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return new SimpleSpiller();
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}
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}
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