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https://github.com/c64scene-ar/llvm-6502.git
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d398672ddd
result type when the result type is legal but not the operand type. Add additional support for EXTRACT_SUBVECTOR and CONCAT_VECTORS, needed to handle such cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57840 91177308-0d34-0410-b5e6-96231b3b80d8
881 lines
32 KiB
C++
881 lines
32 KiB
C++
//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file performs vector type splitting and scalarization for LegalizeTypes.
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// Scalarization is the act of changing a computation in an illegal one-element
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// vector type to be a computation in its scalar element type. For example,
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// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
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// as a base case when scalarizing vector arithmetic like <4 x f32>, which
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// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
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// types.
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// Splitting is the act of changing a computation in an invalid vector type to
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// be a computation in multiple vectors of a smaller type. For example,
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// implementing <128 x f32> operations in terms of two <64 x f32> operations.
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//
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//===----------------------------------------------------------------------===//
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#include "LegalizeTypes.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Result Vector Scalarization: <1 x ty> -> ty.
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//===----------------------------------------------------------------------===//
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void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
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DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
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cerr << "\n");
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SDValue R = SDValue();
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switch (N->getOpcode()) {
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default:
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#ifndef NDEBUG
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cerr << "ScalarizeVectorResult #" << ResNo << ": ";
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N->dump(&DAG); cerr << "\n";
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#endif
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assert(0 && "Do not know how to scalarize the result of this operator!");
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abort();
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case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
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case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
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case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
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case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
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case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
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case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
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case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
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case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
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case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
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case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
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case ISD::CTLZ:
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case ISD::CTPOP:
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case ISD::CTTZ:
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case ISD::FABS:
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case ISD::FCOS:
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case ISD::FNEG:
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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case ISD::FSIN:
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case ISD::FSQRT:
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case ISD::FTRUNC:
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case ISD::FFLOOR:
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case ISD::FCEIL:
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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case ISD::SINT_TO_FP:
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case ISD::TRUNCATE:
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case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
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case ISD::ADD:
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case ISD::AND:
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case ISD::FADD:
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case ISD::FDIV:
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case ISD::FMUL:
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case ISD::FPOW:
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case ISD::FREM:
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case ISD::FSUB:
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case ISD::MUL:
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case ISD::OR:
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case ISD::SDIV:
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case ISD::SREM:
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case ISD::SUB:
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case ISD::UDIV:
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case ISD::UREM:
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case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
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}
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// If R is null, the sub-method took care of registering the result.
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if (R.getNode())
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SetScalarizedVector(SDValue(N, ResNo), R);
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
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SDValue LHS = GetScalarizedVector(N->getOperand(0));
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SDValue RHS = GetScalarizedVector(N->getOperand(1));
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return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
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MVT NewVT = N->getValueType(0).getVectorElementType();
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return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
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N->getValueType(0).getVectorElementType(),
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N->getOperand(0), N->getOperand(1));
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
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SDValue Op = GetScalarizedVector(N->getOperand(0));
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return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
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// The value to insert may have a wider type than the vector element type,
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// so be sure to truncate it to the element type if necessary.
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SDValue Op = N->getOperand(1);
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MVT EltVT = N->getValueType(0).getVectorElementType();
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if (Op.getValueType() != EltVT)
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// FIXME: Can this happen for floating point types?
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Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
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return Op;
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
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assert(N->isUnindexed() && "Indexed vector load?");
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SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getExtensionType(),
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N->getValueType(0).getVectorElementType(),
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N->getChain(), N->getBasePtr(),
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DAG.getNode(ISD::UNDEF,
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N->getBasePtr().getValueType()),
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N->getSrcValue(), N->getSrcValueOffset(),
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N->getMemoryVT().getVectorElementType(),
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N->isVolatile(), N->getAlignment());
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// Legalized the chain result - switch anything that used the old chain to
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// use the new one.
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ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
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return Result;
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
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// Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
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MVT DestVT = N->getValueType(0).getVectorElementType();
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SDValue Op = GetScalarizedVector(N->getOperand(0));
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return DAG.getNode(N->getOpcode(), DestVT, Op);
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
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return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
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SDValue LHS = GetScalarizedVector(N->getOperand(1));
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return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
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GetScalarizedVector(N->getOperand(2)));
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
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// Figure out if the scalar is the LHS or RHS and return it.
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SDValue Arg = N->getOperand(2).getOperand(0);
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if (Arg.getOpcode() == ISD::UNDEF)
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return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
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unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
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return GetScalarizedVector(N->getOperand(Op));
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
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MVT NewVT = N->getValueType(0).getVectorElementType();
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SDValue LHS = GetScalarizedVector(N->getOperand(0));
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SDValue RHS = GetScalarizedVector(N->getOperand(1));
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LHS = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, RHS,
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N->getOperand(2));
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return
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DAG.getNode(ISD::SELECT, NewVT, LHS,
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DAG.getConstant(APInt::getAllOnesValue(NewVT.getSizeInBits()),
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NewVT),
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DAG.getConstant(0ULL, NewVT));
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}
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//===----------------------------------------------------------------------===//
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// Operand Vector Scalarization <1 x ty> -> ty.
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//===----------------------------------------------------------------------===//
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bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
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DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
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cerr << "\n");
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SDValue Res = SDValue();
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if (Res.getNode() == 0) {
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switch (N->getOpcode()) {
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default:
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#ifndef NDEBUG
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cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
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N->dump(&DAG); cerr << "\n";
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#endif
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assert(0 && "Do not know how to scalarize this operator's operand!");
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abort();
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case ISD::BIT_CONVERT:
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Res = ScalarizeVecOp_BIT_CONVERT(N); break;
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case ISD::CONCAT_VECTORS:
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Res = ScalarizeVecOp_CONCAT_VECTORS(N); break;
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case ISD::EXTRACT_VECTOR_ELT:
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Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
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case ISD::STORE:
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Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
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}
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}
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// If the result is null, the sub-method took care of registering results etc.
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if (!Res.getNode()) return false;
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// If the result is N, the sub-method updated N in place. Check to see if any
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// operands are new, and if so, mark them.
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if (Res.getNode() == N) {
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// Mark N as new and remark N and its operands. This allows us to correctly
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// revisit N if it needs another step of promotion and allows us to visit
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// any new operands to N.
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ReanalyzeNode(N);
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return true;
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}
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assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
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"Invalid operand expansion");
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ReplaceValueWith(SDValue(N, 0), Res);
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return false;
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}
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/// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
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/// to be scalarized, it must be <1 x ty>. Convert the element instead.
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SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
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SDValue Elt = GetScalarizedVector(N->getOperand(0));
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return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
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}
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/// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
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/// use a BUILD_VECTOR instead.
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SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
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SmallVector<SDValue, 8> Ops(N->getNumOperands());
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for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
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Ops[i] = GetScalarizedVector(N->getOperand(i));
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return DAG.getNode(ISD::BUILD_VECTOR, N->getValueType(0),
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&Ops[0], Ops.size());
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}
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/// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
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/// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
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/// index.
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SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
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return GetScalarizedVector(N->getOperand(0));
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}
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/// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
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/// scalarized, it must be <1 x ty>. Just store the element.
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SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
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assert(N->isUnindexed() && "Indexed store of one-element vector?");
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assert(OpNo == 1 && "Do not know how to scalarize this operand!");
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if (N->isTruncatingStore())
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return DAG.getTruncStore(N->getChain(),
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GetScalarizedVector(N->getOperand(1)),
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N->getBasePtr(),
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N->getSrcValue(), N->getSrcValueOffset(),
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N->getMemoryVT().getVectorElementType(),
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N->isVolatile(), N->getAlignment());
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return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
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N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
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N->isVolatile(), N->getAlignment());
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}
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//===----------------------------------------------------------------------===//
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// Result Vector Splitting
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//===----------------------------------------------------------------------===//
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/// SplitVectorResult - This method is called when the specified result of the
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/// specified node is found to need vector splitting. At this point, the node
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/// may also have invalid operands or may have other results that need
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/// legalization, we just know that (at least) one result needs vector
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/// splitting.
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void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
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DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
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SDValue Lo, Hi;
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switch (N->getOpcode()) {
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default:
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#ifndef NDEBUG
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cerr << "SplitVectorResult #" << ResNo << ": ";
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N->dump(&DAG); cerr << "\n";
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#endif
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assert(0 && "Do not know how to split the result of this operator!");
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abort();
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case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
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case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
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case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
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case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
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case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
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case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
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case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
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case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
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case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
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case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
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case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
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case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
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case ISD::CTTZ:
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case ISD::CTLZ:
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case ISD::CTPOP:
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case ISD::FNEG:
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case ISD::FABS:
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case ISD::FSQRT:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FTRUNC:
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case ISD::FFLOOR:
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case ISD::FCEIL:
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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case ISD::SINT_TO_FP:
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case ISD::TRUNCATE:
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case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break;
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case ISD::ADD:
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case ISD::SUB:
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case ISD::MUL:
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::FDIV:
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case ISD::FPOW:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::UREM:
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case ISD::SREM:
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case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
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}
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// If Lo/Hi is null, the sub-method took care of registering results etc.
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if (Lo.getNode())
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SetSplitVector(SDValue(N, ResNo), Lo, Hi);
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}
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void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
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SDValue &Hi) {
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SDValue LHSLo, LHSHi;
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GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
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SDValue RHSLo, RHSHi;
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GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
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Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
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Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
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}
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void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
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SDValue &Hi) {
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// We know the result is a vector. The input may be either a vector or a
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// scalar value.
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MVT LoVT, HiVT;
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GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
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SDValue InOp = N->getOperand(0);
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MVT InVT = InOp.getValueType();
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// Handle some special cases efficiently.
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switch (getTypeAction(InVT)) {
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default:
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assert(false && "Unknown type action!");
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case Legal:
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case PromoteInteger:
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case SoftenFloat:
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case ScalarizeVector:
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break;
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case ExpandInteger:
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case ExpandFloat:
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// A scalar to vector conversion, where the scalar needs expansion.
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// If the vector is being split in two then we can just convert the
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// expanded pieces.
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if (LoVT == HiVT) {
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GetExpandedOp(InOp, Lo, Hi);
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if (TLI.isBigEndian())
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std::swap(Lo, Hi);
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Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
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Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
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return;
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}
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break;
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case SplitVector:
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// If the input is a vector that needs to be split, convert each split
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// piece of the input now.
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GetSplitVector(InOp, Lo, Hi);
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Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
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Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
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return;
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}
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// In the general case, convert the input to an integer and split it by hand.
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MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
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MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
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if (TLI.isBigEndian())
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std::swap(LoIntVT, HiIntVT);
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SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
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if (TLI.isBigEndian())
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std::swap(Lo, Hi);
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Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
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Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
|
|
}
|
|
|
|
void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
|
|
SDValue &Hi) {
|
|
MVT LoVT, HiVT;
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
|
unsigned LoNumElts = LoVT.getVectorNumElements();
|
|
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
|
|
Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
|
|
|
|
SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
|
|
Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
|
|
}
|
|
|
|
void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
|
|
SDValue &Hi) {
|
|
assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
|
|
unsigned NumSubvectors = N->getNumOperands() / 2;
|
|
if (NumSubvectors == 1) {
|
|
Lo = N->getOperand(0);
|
|
Hi = N->getOperand(1);
|
|
return;
|
|
}
|
|
|
|
MVT LoVT, HiVT;
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
|
|
|
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
|
|
Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
|
|
|
|
SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
|
|
Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
|
|
}
|
|
|
|
void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
|
|
SDValue &Hi) {
|
|
GetSplitVector(N->getOperand(0), Lo, Hi);
|
|
Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
|
|
Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
|
|
}
|
|
|
|
void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
|
|
SDValue &Hi) {
|
|
SDValue Vec = N->getOperand(0);
|
|
SDValue Elt = N->getOperand(1);
|
|
SDValue Idx = N->getOperand(2);
|
|
GetSplitVector(Vec, Lo, Hi);
|
|
|
|
if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
|
|
unsigned IdxVal = CIdx->getZExtValue();
|
|
unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
|
|
if (IdxVal < LoNumElts)
|
|
Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
|
|
else
|
|
Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt,
|
|
DAG.getIntPtrConstant(IdxVal - LoNumElts));
|
|
return;
|
|
}
|
|
|
|
// Spill the vector to the stack.
|
|
MVT VecVT = Vec.getValueType();
|
|
MVT EltVT = VecVT.getVectorElementType();
|
|
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
|
|
SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
|
|
|
|
// Store the new element. This may be larger than the vector element type,
|
|
// so use a truncating store.
|
|
SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
|
|
Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
|
|
|
|
// Reload the vector from the stack.
|
|
SDValue Load = DAG.getLoad(VecVT, Store, StackPtr, NULL, 0);
|
|
|
|
// Split it.
|
|
SplitVecRes_LOAD(cast<LoadSDNode>(Load.getNode()), Lo, Hi);
|
|
}
|
|
|
|
void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
|
|
SDValue &Hi) {
|
|
assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
|
|
MVT LoVT, HiVT;
|
|
GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
|
|
|
|
ISD::LoadExtType ExtType = LD->getExtensionType();
|
|
SDValue Ch = LD->getChain();
|
|
SDValue Ptr = LD->getBasePtr();
|
|
SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
|
|
const Value *SV = LD->getSrcValue();
|
|
int SVOffset = LD->getSrcValueOffset();
|
|
MVT MemoryVT = LD->getMemoryVT();
|
|
unsigned Alignment = LD->getAlignment();
|
|
bool isVolatile = LD->isVolatile();
|
|
|
|
MVT LoMemVT, HiMemVT;
|
|
GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
|
|
|
|
Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, Ch, Ptr, Offset,
|
|
SV, SVOffset, LoMemVT, isVolatile, Alignment);
|
|
|
|
unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
|
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
|
DAG.getIntPtrConstant(IncrementSize));
|
|
SVOffset += IncrementSize;
|
|
Alignment = MinAlign(Alignment, IncrementSize);
|
|
Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, Ch, Ptr, Offset,
|
|
SV, SVOffset, HiMemVT, isVolatile, Alignment);
|
|
|
|
// Build a factor node to remember that this load is independent of the
|
|
// other one.
|
|
Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
|
|
Hi.getValue(1));
|
|
|
|
// Legalized the chain result - switch anything that used the old chain to
|
|
// use the new one.
|
|
ReplaceValueWith(SDValue(LD, 1), Ch);
|
|
}
|
|
|
|
void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
|
|
SDValue &Hi) {
|
|
// Get the dest types - they may not match the input types, e.g. int_to_fp.
|
|
MVT LoVT, HiVT;
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
|
|
|
// Split the input.
|
|
MVT InVT = N->getOperand(0).getValueType();
|
|
switch (getTypeAction(InVT)) {
|
|
default: assert(0 && "Unexpected type action!");
|
|
case Legal: {
|
|
assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
|
|
MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
|
|
LoVT.getVectorNumElements());
|
|
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
|
|
DAG.getIntPtrConstant(0));
|
|
Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
|
|
DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
|
|
break;
|
|
}
|
|
case SplitVector:
|
|
GetSplitVector(N->getOperand(0), Lo, Hi);
|
|
break;
|
|
}
|
|
|
|
Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
|
|
Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
|
|
}
|
|
|
|
void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
|
|
SDValue &Hi) {
|
|
// Build the low part.
|
|
SDValue Mask = N->getOperand(2);
|
|
SmallVector<SDValue, 16> Ops;
|
|
MVT LoVT, HiVT;
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
|
MVT EltVT = LoVT.getVectorElementType();
|
|
unsigned LoNumElts = LoVT.getVectorNumElements();
|
|
unsigned NumElements = Mask.getNumOperands();
|
|
|
|
// Insert all of the elements from the input that are needed. We use
|
|
// buildvector of extractelement here because the input vectors will have
|
|
// to be legalized, so this makes the code simpler.
|
|
for (unsigned i = 0; i != LoNumElts; ++i) {
|
|
SDValue Arg = Mask.getOperand(i);
|
|
if (Arg.getOpcode() == ISD::UNDEF) {
|
|
Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
|
|
} else {
|
|
unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
|
|
SDValue InVec = N->getOperand(0);
|
|
if (Idx >= NumElements) {
|
|
InVec = N->getOperand(1);
|
|
Idx -= NumElements;
|
|
}
|
|
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
|
|
DAG.getIntPtrConstant(Idx)));
|
|
}
|
|
}
|
|
Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &Ops[0], Ops.size());
|
|
Ops.clear();
|
|
|
|
for (unsigned i = LoNumElts; i != NumElements; ++i) {
|
|
unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getZExtValue();
|
|
SDValue InVec = N->getOperand(0);
|
|
if (Idx >= NumElements) {
|
|
InVec = N->getOperand(1);
|
|
Idx -= NumElements;
|
|
}
|
|
Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, InVec,
|
|
DAG.getIntPtrConstant(Idx)));
|
|
}
|
|
Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &Ops[0], Ops.size());
|
|
}
|
|
|
|
void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
|
|
SDValue &Hi) {
|
|
MVT LoVT, HiVT;
|
|
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
|
|
|
|
SDValue LL, LH, RL, RH;
|
|
GetSplitVector(N->getOperand(0), LL, LH);
|
|
GetSplitVector(N->getOperand(1), RL, RH);
|
|
|
|
Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
|
|
Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Operand Vector Splitting
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// SplitVectorOperand - This method is called when the specified operand of the
|
|
/// specified node is found to need vector splitting. At this point, all of the
|
|
/// result types of the node are known to be legal, but other operands of the
|
|
/// node may need legalization as well as the specified one.
|
|
bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
|
|
DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
|
|
SDValue Res = SDValue();
|
|
|
|
if (Res.getNode() == 0) {
|
|
switch (N->getOpcode()) {
|
|
default:
|
|
#ifndef NDEBUG
|
|
cerr << "SplitVectorOperand Op #" << OpNo << ": ";
|
|
N->dump(&DAG); cerr << "\n";
|
|
#endif
|
|
assert(0 && "Do not know how to split this operator's operand!");
|
|
abort();
|
|
|
|
case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
|
|
case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
|
|
case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
|
|
case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
|
|
OpNo); break;
|
|
case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
|
|
|
|
case ISD::CTTZ:
|
|
case ISD::CTLZ:
|
|
case ISD::CTPOP:
|
|
case ISD::FP_TO_SINT:
|
|
case ISD::FP_TO_UINT:
|
|
case ISD::SINT_TO_FP:
|
|
case ISD::TRUNCATE:
|
|
case ISD::UINT_TO_FP: Res = SplitVecOp_UnaryOp(N); break;
|
|
}
|
|
}
|
|
|
|
// If the result is null, the sub-method took care of registering results etc.
|
|
if (!Res.getNode()) return false;
|
|
|
|
// If the result is N, the sub-method updated N in place. Check to see if any
|
|
// operands are new, and if so, mark them.
|
|
if (Res.getNode() == N) {
|
|
// Mark N as new and remark N and its operands. This allows us to correctly
|
|
// revisit N if it needs another step of promotion and allows us to visit
|
|
// any new operands to N.
|
|
ReanalyzeNode(N);
|
|
return true;
|
|
}
|
|
|
|
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
|
|
"Invalid operand expansion");
|
|
|
|
ReplaceValueWith(SDValue(N, 0), Res);
|
|
return false;
|
|
}
|
|
|
|
SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
|
|
// The result has a legal vector type, but the input needs splitting.
|
|
MVT ResVT = N->getValueType(0);
|
|
SDValue Lo, Hi;
|
|
GetSplitVector(N->getOperand(0), Lo, Hi);
|
|
assert(Lo.getValueType() == Hi.getValueType() &&
|
|
"Returns legal non-power-of-two vector type?");
|
|
MVT InVT = Lo.getValueType();
|
|
|
|
MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
|
|
InVT.getVectorNumElements());
|
|
|
|
Lo = DAG.getNode(N->getOpcode(), OutVT, Lo);
|
|
Hi = DAG.getNode(N->getOpcode(), OutVT, Hi);
|
|
|
|
return DAG.getNode(ISD::CONCAT_VECTORS, ResVT, Lo, Hi);
|
|
}
|
|
|
|
SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
|
|
// For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
|
|
// end up being split all the way down to individual components. Convert the
|
|
// split pieces into integers and reassemble.
|
|
SDValue Lo, Hi;
|
|
GetSplitVector(N->getOperand(0), Lo, Hi);
|
|
Lo = BitConvertToInteger(Lo);
|
|
Hi = BitConvertToInteger(Hi);
|
|
|
|
if (TLI.isBigEndian())
|
|
std::swap(Lo, Hi);
|
|
|
|
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
|
|
JoinIntegers(Lo, Hi));
|
|
}
|
|
|
|
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
|
|
// We know that the extracted result type is legal. For now, assume the index
|
|
// is a constant.
|
|
MVT SubVT = N->getValueType(0);
|
|
SDValue Idx = N->getOperand(1);
|
|
SDValue Lo, Hi;
|
|
GetSplitVector(N->getOperand(0), Lo, Hi);
|
|
|
|
uint64_t LoElts = Lo.getValueType().getVectorNumElements();
|
|
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
|
|
|
|
if (IdxVal < LoElts) {
|
|
assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
|
|
"Extracted subvector crosses vector split!");
|
|
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
|
|
} else {
|
|
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
|
|
DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
|
|
}
|
|
}
|
|
|
|
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
|
|
SDValue Vec = N->getOperand(0);
|
|
SDValue Idx = N->getOperand(1);
|
|
MVT VecVT = Vec.getValueType();
|
|
|
|
if (isa<ConstantSDNode>(Idx)) {
|
|
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
|
|
assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
|
|
|
|
SDValue Lo, Hi;
|
|
GetSplitVector(Vec, Lo, Hi);
|
|
|
|
uint64_t LoElts = Lo.getValueType().getVectorNumElements();
|
|
|
|
if (IdxVal < LoElts)
|
|
return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
|
|
else
|
|
return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
|
|
DAG.getConstant(IdxVal - LoElts,
|
|
Idx.getValueType()));
|
|
}
|
|
|
|
// Store the vector to the stack.
|
|
MVT EltVT = VecVT.getVectorElementType();
|
|
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
|
|
SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
|
|
|
|
// Load back the required element.
|
|
StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
|
|
return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
|
|
}
|
|
|
|
SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
|
|
assert(N->isUnindexed() && "Indexed store of vector?");
|
|
assert(OpNo == 1 && "Can only split the stored value");
|
|
|
|
bool isTruncating = N->isTruncatingStore();
|
|
SDValue Ch = N->getChain();
|
|
SDValue Ptr = N->getBasePtr();
|
|
int SVOffset = N->getSrcValueOffset();
|
|
MVT MemoryVT = N->getMemoryVT();
|
|
unsigned Alignment = N->getAlignment();
|
|
bool isVol = N->isVolatile();
|
|
SDValue Lo, Hi;
|
|
GetSplitVector(N->getOperand(1), Lo, Hi);
|
|
|
|
MVT LoMemVT, HiMemVT;
|
|
GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
|
|
|
|
unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
|
|
|
|
if (isTruncating)
|
|
Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
|
|
LoMemVT, isVol, Alignment);
|
|
else
|
|
Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
|
|
isVol, Alignment);
|
|
|
|
// Increment the pointer to the other half.
|
|
Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
|
|
DAG.getIntPtrConstant(IncrementSize));
|
|
|
|
if (isTruncating)
|
|
Hi = DAG.getTruncStore(Ch, Hi, Ptr,
|
|
N->getSrcValue(), SVOffset+IncrementSize,
|
|
HiMemVT,
|
|
isVol, MinAlign(Alignment, IncrementSize));
|
|
else
|
|
Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
|
|
isVol, MinAlign(Alignment, IncrementSize));
|
|
|
|
return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
|
|
}
|
|
|
|
SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
|
|
assert(OpNo == 2 && "Shuffle source type differs from result type?");
|
|
SDValue Mask = N->getOperand(2);
|
|
unsigned MaskLength = Mask.getValueType().getVectorNumElements();
|
|
unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
|
|
unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
|
|
|
|
// Look for a legal vector type to place the mask values in.
|
|
// Note that there may not be *any* legal vector-of-integer
|
|
// type for which the element type is legal!
|
|
for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
|
|
EltVT <= MVT::LAST_INTEGER_VALUETYPE;
|
|
// Integer values types are consecutively numbered. Exploit this.
|
|
EltVT = MVT::SimpleValueType(EltVT + 1)) {
|
|
|
|
// Is the element type big enough to hold the values?
|
|
if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
|
|
// Nope.
|
|
continue;
|
|
|
|
// Is the vector type legal?
|
|
MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
|
|
if (!isTypeLegal(VecVT))
|
|
// Nope.
|
|
continue;
|
|
|
|
// If the element type is not legal, find a larger legal type to use for
|
|
// the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
|
|
// FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
|
|
// node where the shuffle mask is a list of integer operands, #2 .. #2+n.
|
|
for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
|
|
// Integer values types are consecutively numbered. Exploit this.
|
|
OpVT = MVT::SimpleValueType(OpVT + 1)) {
|
|
if (!isTypeLegal(OpVT))
|
|
continue;
|
|
|
|
// Success! Rebuild the vector using the legal types.
|
|
SmallVector<SDValue, 16> Ops(MaskLength);
|
|
for (unsigned i = 0; i < MaskLength; ++i) {
|
|
SDValue Arg = Mask.getOperand(i);
|
|
if (Arg.getOpcode() == ISD::UNDEF) {
|
|
Ops[i] = DAG.getNode(ISD::UNDEF, OpVT);
|
|
} else {
|
|
uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
|
|
Ops[i] = DAG.getConstant(Idx, OpVT);
|
|
}
|
|
}
|
|
return DAG.UpdateNodeOperands(SDValue(N,0),
|
|
N->getOperand(0), N->getOperand(1),
|
|
DAG.getNode(ISD::BUILD_VECTOR,
|
|
VecVT, &Ops[0], Ops.size()));
|
|
}
|
|
|
|
// Continuing is pointless - failure is certain.
|
|
break;
|
|
}
|
|
assert(false && "Failed to find an appropriate mask type!");
|
|
return SDValue(N, 0);
|
|
}
|