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069287d460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28324 91177308-0d34-0410-b5e6-96231b3b80d8
178 lines
7.4 KiB
C++
178 lines
7.4 KiB
C++
//===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 Register file, defining the registers themselves,
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// aliases between the registers, and the register classes built out of the
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// registers.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register definitions...
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//
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let Namespace = "X86" in {
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// In the register alias definitions below, we define which registers alias
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// which others. We only specify which registers the small registers alias,
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// because the register file generator is smart enough to figure out that
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// AL aliases AX if we tell it that AX aliased AL (for example).
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// 32-bit registers
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def EAX : Register<"EAX">, DwarfRegNum<0>;
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def ECX : Register<"ECX">, DwarfRegNum<2>;
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def EDX : Register<"EDX">, DwarfRegNum<1>;
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def EBX : Register<"EBX">, DwarfRegNum<3>;
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def ESP : Register<"ESP">, DwarfRegNum<7>;
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def EBP : Register<"EBP">, DwarfRegNum<6>;
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def ESI : Register<"ESI">, DwarfRegNum<4>;
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def EDI : Register<"EDI">, DwarfRegNum<5>;
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// 16-bit registers
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def AX : RegisterGroup<"AX", [EAX]>, DwarfRegNum<0>;
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def CX : RegisterGroup<"CX", [ECX]>, DwarfRegNum<2>;
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def DX : RegisterGroup<"DX", [EDX]>, DwarfRegNum<1>;
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def BX : RegisterGroup<"BX", [EBX]>, DwarfRegNum<3>;
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def SP : RegisterGroup<"SP", [ESP]>, DwarfRegNum<7>;
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def BP : RegisterGroup<"BP", [EBP]>, DwarfRegNum<6>;
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def SI : RegisterGroup<"SI", [ESI]>, DwarfRegNum<4>;
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def DI : RegisterGroup<"DI", [EDI]>, DwarfRegNum<5>;
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// 8-bit registers
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def AL : RegisterGroup<"AL", [AX,EAX]>, DwarfRegNum<0>;
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def CL : RegisterGroup<"CL", [CX,ECX]>, DwarfRegNum<2>;
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def DL : RegisterGroup<"DL", [DX,EDX]>, DwarfRegNum<1>;
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def BL : RegisterGroup<"BL", [BX,EBX]>, DwarfRegNum<3>;
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def AH : RegisterGroup<"AH", [AX,EAX]>, DwarfRegNum<0>;
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def CH : RegisterGroup<"CH", [CX,ECX]>, DwarfRegNum<2>;
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def DH : RegisterGroup<"DH", [DX,EDX]>, DwarfRegNum<1>;
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def BH : RegisterGroup<"BH", [BX,EBX]>, DwarfRegNum<3>;
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// MMX Registers. These are actually aliased to ST0 .. ST7
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def MM0 : Register<"MM0">, DwarfRegNum<29>;
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def MM1 : Register<"MM1">, DwarfRegNum<30>;
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def MM2 : Register<"MM2">, DwarfRegNum<31>;
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def MM3 : Register<"MM3">, DwarfRegNum<32>;
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def MM4 : Register<"MM4">, DwarfRegNum<33>;
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def MM5 : Register<"MM5">, DwarfRegNum<34>;
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def MM6 : Register<"MM6">, DwarfRegNum<35>;
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def MM7 : Register<"MM7">, DwarfRegNum<36>;
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// Pseudo Floating Point registers
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def FP0 : Register<"FP0">, DwarfRegNum<-1>;
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def FP1 : Register<"FP1">, DwarfRegNum<-1>;
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def FP2 : Register<"FP2">, DwarfRegNum<-1>;
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def FP3 : Register<"FP3">, DwarfRegNum<-1>;
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def FP4 : Register<"FP4">, DwarfRegNum<-1>;
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def FP5 : Register<"FP5">, DwarfRegNum<-1>;
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def FP6 : Register<"FP6">, DwarfRegNum<-1>;
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// XMM Registers, used by the various SSE instruction set extensions
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def XMM0: Register<"XMM0">, DwarfRegNum<21>;
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def XMM1: Register<"XMM1">, DwarfRegNum<22>;
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def XMM2: Register<"XMM2">, DwarfRegNum<23>;
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def XMM3: Register<"XMM3">, DwarfRegNum<24>;
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def XMM4: Register<"XMM4">, DwarfRegNum<25>;
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def XMM5: Register<"XMM5">, DwarfRegNum<26>;
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def XMM6: Register<"XMM6">, DwarfRegNum<27>;
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def XMM7: Register<"XMM7">, DwarfRegNum<28>;
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// Floating point stack registers
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def ST0 : Register<"ST(0)">, DwarfRegNum<8>;
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def ST1 : Register<"ST(1)">, DwarfRegNum<9>;
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def ST2 : Register<"ST(2)">, DwarfRegNum<10>;
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def ST3 : Register<"ST(3)">, DwarfRegNum<11>;
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def ST4 : Register<"ST(4)">, DwarfRegNum<12>;
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def ST5 : Register<"ST(5)">, DwarfRegNum<13>;
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def ST6 : Register<"ST(6)">, DwarfRegNum<14>;
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def ST7 : Register<"ST(7)">, DwarfRegNum<15>;
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}
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//===----------------------------------------------------------------------===//
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// Register Class Definitions... now that we have all of the pieces, define the
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// top-level register classes. The order specified in the register list is
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// implicitly defined to be the register allocation order.
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//
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// List AL,CL,DL before AH,CH,DH, as X86 processors often suffer from false
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// dependences between upper and lower parts of the register. BL and BH are
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// last because they are call clobbered. Both Athlon and P4 chips suffer this
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// issue.
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def GR8 : RegisterClass<"X86", [i8], 8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
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def GR16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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GR16Class::iterator
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GR16Class::allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
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return end()-2; // If so, don't allocate SP or BP
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else
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return end()-1; // If not, just don't allocate SP
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}
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}];
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}
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def GR32 : RegisterClass<"X86", [i32], 32,
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[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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GR32Class::iterator
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GR32Class::allocation_order_end(MachineFunction &MF) const {
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if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
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return end()-2; // If so, don't allocate ESP or EBP
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else
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return end()-1; // If not, just don't allocate ESP
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}
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}];
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}
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// GR16, GR32 subclasses which contain registers that have R8 sub-registers.
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def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]>;
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def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]>;
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// Scalar SSE2 floating point registers.
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def FR32 : RegisterClass<"X86", [f32], 32,
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
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def FR64 : RegisterClass<"X86", [f64], 64,
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
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// FIXME: This sets up the floating point register files as though they are f64
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// values, though they really are f80 values. This will cause us to spill
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// values as 64-bit quantities instead of 80-bit quantities, which is much much
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// faster on common hardware. In reality, this should be controlled by a
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// command line option or something.
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def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
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// Floating point stack registers (these are not allocatable by the
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// register allocator - the floating point stackifier is responsible
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// for transforming FPn allocations to STn registers)
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def RST : RegisterClass<"X86", [f64], 32,
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[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
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let MethodProtos = [{
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iterator allocation_order_end(MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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RSTClass::iterator
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RSTClass::allocation_order_end(MachineFunction &MF) const {
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return begin();
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}
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}];
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}
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// Generic vector registers: VR64 and VR128.
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def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32], 64,
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[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
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def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
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[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
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