llvm-6502/lib/Target/SparcV8
2004-11-17 22:06:56 +00:00
..
DelaySlotFiller.cpp Use TargetMachine::hasDelaySlot() instead of our old switch statement 2004-09-30 04:04:47 +00:00
FPMover.cpp Pass which converts FpMOVD (double move pseudoinstructions) to pairs 2004-09-29 03:24:34 +00:00
Makefile Change name of target lib to conform to new naming scheme. 2004-10-29 21:57:16 +00:00
README.txt Update list of failing benchmarks 2004-11-16 07:32:58 +00:00
SparcV8.h Add createSparcV8FPMoverPass(). 2004-09-29 03:25:39 +00:00
SparcV8.td Prettify formatting of the file, adjust paths to making V8 a subdir of Sparc 2004-09-22 20:09:29 +00:00
SparcV8AsmPrinter.cpp Support UndefValue emission. 2004-11-14 03:22:05 +00:00
SparcV8CodeEmitter.cpp * Add baseline structural JIT code, but disable the JIT to allow llvm-gcc builds 2004-10-19 19:49:42 +00:00
SparcV8InstrFormats.td Class F2_1 already inherits the imm22 field from class F2 2004-10-14 22:32:24 +00:00
SparcV8InstrInfo.cpp Recognize FpMOVD as a move. 2004-09-29 16:45:47 +00:00
SparcV8InstrInfo.h I think that V8 should coallesce registers, don't you? 2004-07-25 06:19:04 +00:00
SparcV8InstrInfo.td Correct the implicit-defs information for indirect and direct calls. 2004-11-16 07:32:09 +00:00
SparcV8ISelSimple.cpp We were (somehow) getting the wrong branch opcode for setcc float instrs. 2004-11-17 22:06:56 +00:00
SparcV8JITInfo.h
SparcV8RegisterInfo.cpp Remove dependency on MRegisterInfo::getRegClass 2004-10-29 21:42:27 +00:00
SparcV8RegisterInfo.h Code insertion methods now return void instead of an int. 2004-08-15 22:15:11 +00:00
SparcV8RegisterInfo.td SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned! 2004-09-27 18:22:18 +00:00
SparcV8TargetMachine.cpp Implement getModuleMatchQuality and getJITMatchQuality so that v8 will be the 2004-10-09 05:57:01 +00:00
SparcV8TargetMachine.h Implement getModuleMatchQuality and getJITMatchQuality so that v8 will be the 2004-10-09 05:57:01 +00:00

SparcV8 backend skeleton
------------------------

This directory houses a 32-bit SPARC V8 backend employing a expander-based
instruction selector.  It is not yet functionally complete.  Watch
this space for more news coming soon!

Current expected test failures
------------------------------

SingleSource/Benchmarks (excluding C++ tests): 
fldry heapsort misr pi

SingleSource/UnitTests:
C++Catch SimpleC++Test 2003-05-07-VarArgs 2003-07-09-SignedArgs
2003-08-11-VaListArg

To-do
-----

* support calling functions with more than 6 args
* support 64-bit integer (long, ulong) arguments to functions
  - use libc procedures instead of open-coding for:
    __div64 __mul64 __rem64 __udiv64 __umul64 __urem64
* support setcc on longs
* support basic binary operations on longs
* support casting <=32-bit integers, bools to long
* support casting 64-bit integers to FP types
* support varargs intrinsics (va_start et al.)

$Date$