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https://github.com/c64scene-ar/llvm-6502.git
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b3f912b510
r186399 aggressively used the RISBG instruction for immediate ANDs, both because it can handle some values that AND IMMEDIATE can't, and because it allows the destination register to be different from the source. I realized later while implementing the distinct-ops support that it would be better to leave the choice up to convertToThreeAddress() instead. The AND IMMEDIATE form is shorter and is less likely to be cracked. This is a problem for 32-bit ANDs because we assume that all 32-bit operations will leave the high word untouched, whereas RISBG used in this way will either clear the high word or copy it from the source register. The patch uses the z196 instruction RISBLG for this instead. This means that z10 will be restricted to NILL, NILH and NILF for 32-bit ANDs, but I think that should be OK for now. Although we're using z10 as the base architecture, the optimization work is going to be focused more on z196 and zEC12. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187492 91177308-0d34-0410-b5e6-96231b3b80d8
56 lines
1.9 KiB
LLVM
56 lines
1.9 KiB
LLVM
; Test 8-bit atomic exchange.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT
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; Check exchange with a variable.
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; - CHECK is for the main loop.
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; - CHECK-SHIFT makes sure that the negated shift count used by the second
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; RLL is set up correctly. The negation is independent of the NILL and L
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; tested in CHECK. CHECK-SHIFT also checks that %r3 is not modified before
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; being used in the RISBG (in contrast to things like atomic addition,
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; which shift %r3 left so that %b is at the high end of the word).
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define i8 @f1(i8 *%src, i8 %b) {
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; CHECK-LABEL: f1:
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; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK: nill %r2, 65532
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; CHECK: l [[OLD:%r[0-9]+]], 0(%r2)
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; CHECK: [[LABEL:\.[^:]*]]:
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; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
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; CHECK: risbg [[ROT]], %r3, 32, 39, 24
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; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
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; CHECK: cs [[OLD]], [[NEW]], 0(%r2)
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; CHECK: jlh [[LABEL]]
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; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
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; CHECK: br %r14
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;
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; CHECK-SHIFT-LABEL: f1:
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; CHECK-SHIFT-NOT: %r3
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; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3
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; CHECK-SHIFT-NOT: %r3
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; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
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; CHECK-SHIFT-NOT: %r3
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; CHECK-SHIFT: rll
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; CHECK-SHIFT-NOT: %r3
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; CHECK-SHIFT: risbg {{%r[0-9]+}}, %r3, 32, 39, 24
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; CHECK-SHIFT: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
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; CHECK-SHIFT: rll
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; CHECK-SHIFT: br %r14
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%res = atomicrmw xchg i8 *%src, i8 %b seq_cst
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ret i8 %res
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}
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; Check exchange with a constant. We should force the constant into
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; a register and use the sequence above.
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define i8 @f2(i8 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: lhi [[VALUE:%r[0-9]+]], 88
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; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 39, 24
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; CHECK: br %r14
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;
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; CHECK-SHIFT-LABEL: f2:
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; CHECK-SHIFT: br %r14
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%res = atomicrmw xchg i8 *%src, i8 88 seq_cst
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ret i8 %res
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}
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