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b3fa233048
Summary: Add a second fixup table to MipsAsmBackend::getFixupKindInfo() to correctly position llvm-mc's fixup placeholders for big-endian. See PR19836 for full details of the issue. To summarize, the fixup placeholders do not account for endianness properly and the implementations of getFixupKindInfo() for each target are measuring MCFixupKindInfo.TargetOffset from different ends of the instruction encoding to compensate. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3889 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209514 91177308-0d34-0410-b5e6-96231b3b80d8
382 lines
15 KiB
C++
382 lines
15 KiB
C++
//===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MipsAsmBackend class.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "MCTargetDesc/MipsFixupKinds.h"
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#include "MCTargetDesc/MipsAsmBackend.h"
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// Prepare value for the target space for it
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static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
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MCContext *Ctx = nullptr) {
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unsigned Kind = Fixup.getKind();
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// Add/subtract and shift
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switch (Kind) {
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default:
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return 0;
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case FK_Data_2:
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case FK_GPRel_4:
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case FK_Data_4:
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case FK_Data_8:
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case Mips::fixup_Mips_LO16:
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case Mips::fixup_Mips_GPREL16:
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case Mips::fixup_Mips_GPOFF_HI:
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case Mips::fixup_Mips_GPOFF_LO:
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case Mips::fixup_Mips_GOT_PAGE:
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case Mips::fixup_Mips_GOT_OFST:
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case Mips::fixup_Mips_GOT_DISP:
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case Mips::fixup_Mips_GOT_LO16:
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case Mips::fixup_Mips_CALL_LO16:
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case Mips::fixup_MICROMIPS_LO16:
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case Mips::fixup_MICROMIPS_GOT_PAGE:
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case Mips::fixup_MICROMIPS_GOT_OFST:
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case Mips::fixup_MICROMIPS_GOT_DISP:
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break;
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case Mips::fixup_Mips_PC16:
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// So far we are only using this type for branches.
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// For branches we start 1 instruction after the branch
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// so the displacement will be one instruction size less.
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Value -= 4;
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// The displacement is then divided by 4 to give us an 18 bit
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// address range. Forcing a signed division because Value can be negative.
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Value = (int64_t)Value / 4;
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// We now check if Value can be encoded as a 16-bit signed immediate.
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if (!isIntN(16, Value) && Ctx)
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Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
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break;
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case Mips::fixup_Mips_26:
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// So far we are only using this type for jumps.
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// The displacement is then divided by 4 to give us an 28 bit
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// address range.
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Value >>= 2;
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break;
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case Mips::fixup_Mips_HI16:
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case Mips::fixup_Mips_GOT_Local:
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case Mips::fixup_Mips_GOT_HI16:
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case Mips::fixup_Mips_CALL_HI16:
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case Mips::fixup_MICROMIPS_HI16:
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// Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
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Value = ((Value + 0x8000) >> 16) & 0xffff;
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break;
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case Mips::fixup_Mips_HIGHER:
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// Get the 3rd 16-bits.
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Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
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break;
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case Mips::fixup_Mips_HIGHEST:
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// Get the 4th 16-bits.
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Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
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break;
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case Mips::fixup_MICROMIPS_26_S1:
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Value >>= 1;
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break;
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case Mips::fixup_MICROMIPS_PC16_S1:
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Value -= 4;
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// Forcing a signed division because Value can be negative.
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Value = (int64_t)Value / 2;
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// We now check if Value can be encoded as a 16-bit signed immediate.
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if (!isIntN(16, Value) && Ctx)
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Ctx->FatalError(Fixup.getLoc(), "out of range PC16 fixup");
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break;
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}
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return Value;
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}
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MCObjectWriter *MipsAsmBackend::createObjectWriter(raw_ostream &OS) const {
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return createMipsELFObjectWriter(OS,
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MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
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}
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// Little-endian fixup data byte ordering:
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// mips32r2: a | b | x | x
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// microMIPS: x | x | a | b
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static bool needsMMLEByteOrder(unsigned Kind) {
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return Kind >= Mips::fixup_MICROMIPS_26_S1 &&
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Kind < Mips::LastTargetFixupKind;
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}
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// Calculate index for microMIPS specific little endian byte order
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static unsigned calculateMMLEIndex(unsigned i) {
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assert(i <= 3 && "Index out of range!");
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return (1 - i / 2) * 2 + i % 2;
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}
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/// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
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/// data fragment, at the offset specified by the fixup and following the
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/// fixup kind as appropriate.
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void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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unsigned DataSize, uint64_t Value,
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bool IsPCRel) const {
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MCFixupKind Kind = Fixup.getKind();
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Value = adjustFixupValue(Fixup, Value);
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if (!Value)
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return; // Doesn't change encoding.
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// Where do we start in the object
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unsigned Offset = Fixup.getOffset();
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// Number of bytes we need to fixup
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unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
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// Used to point to big endian bytes
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unsigned FullSize;
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switch ((unsigned)Kind) {
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case FK_Data_2:
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case Mips::fixup_Mips_16:
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FullSize = 2;
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break;
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case FK_Data_8:
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case Mips::fixup_Mips_64:
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FullSize = 8;
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break;
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case FK_Data_4:
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default:
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FullSize = 4;
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break;
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}
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// Grab current value, if any, from bits.
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uint64_t CurVal = 0;
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bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind);
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for (unsigned i = 0; i != NumBytes; ++i) {
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unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
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: i)
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: (FullSize - 1 - i);
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CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
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}
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uint64_t Mask = ((uint64_t)(-1) >>
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(64 - getFixupKindInfo(Kind).TargetSize));
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CurVal |= Value & Mask;
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// Write out the fixed up bytes back to the code/data bits.
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for (unsigned i = 0; i != NumBytes; ++i) {
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unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
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: i)
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: (FullSize - 1 - i);
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Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
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}
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}
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const MCFixupKindInfo &MipsAsmBackend::
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getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
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// This table *must* be in same the order of fixup_* kinds in
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// MipsFixupKinds.h.
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//
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// name offset bits flags
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{ "fixup_Mips_16", 0, 16, 0 },
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{ "fixup_Mips_32", 0, 32, 0 },
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{ "fixup_Mips_REL32", 0, 32, 0 },
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{ "fixup_Mips_26", 0, 26, 0 },
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{ "fixup_Mips_HI16", 0, 16, 0 },
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{ "fixup_Mips_LO16", 0, 16, 0 },
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{ "fixup_Mips_GPREL16", 0, 16, 0 },
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{ "fixup_Mips_LITERAL", 0, 16, 0 },
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{ "fixup_Mips_GOT_Global", 0, 16, 0 },
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{ "fixup_Mips_GOT_Local", 0, 16, 0 },
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{ "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_Mips_CALL16", 0, 16, 0 },
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{ "fixup_Mips_GPREL32", 0, 32, 0 },
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{ "fixup_Mips_SHIFT5", 6, 5, 0 },
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{ "fixup_Mips_SHIFT6", 6, 5, 0 },
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{ "fixup_Mips_64", 0, 64, 0 },
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{ "fixup_Mips_TLSGD", 0, 16, 0 },
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{ "fixup_Mips_GOTTPREL", 0, 16, 0 },
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{ "fixup_Mips_TPREL_HI", 0, 16, 0 },
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{ "fixup_Mips_TPREL_LO", 0, 16, 0 },
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{ "fixup_Mips_TLSLDM", 0, 16, 0 },
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{ "fixup_Mips_DTPREL_HI", 0, 16, 0 },
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{ "fixup_Mips_DTPREL_LO", 0, 16, 0 },
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{ "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_Mips_GPOFF_HI", 0, 16, 0 },
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{ "fixup_Mips_GPOFF_LO", 0, 16, 0 },
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{ "fixup_Mips_GOT_PAGE", 0, 16, 0 },
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{ "fixup_Mips_GOT_OFST", 0, 16, 0 },
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{ "fixup_Mips_GOT_DISP", 0, 16, 0 },
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{ "fixup_Mips_HIGHER", 0, 16, 0 },
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{ "fixup_Mips_HIGHEST", 0, 16, 0 },
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{ "fixup_Mips_GOT_HI16", 0, 16, 0 },
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{ "fixup_Mips_GOT_LO16", 0, 16, 0 },
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{ "fixup_Mips_CALL_HI16", 0, 16, 0 },
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{ "fixup_Mips_CALL_LO16", 0, 16, 0 },
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{ "fixup_MICROMIPS_26_S1", 0, 26, 0 },
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{ "fixup_MICROMIPS_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_LO16", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT16", 0, 16, 0 },
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{ "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_CALL16", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
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{ "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
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{ "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }
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};
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const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
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// This table *must* be in same the order of fixup_* kinds in
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// MipsFixupKinds.h.
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//
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// name offset bits flags
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{ "fixup_Mips_16", 16, 16, 0 },
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{ "fixup_Mips_32", 0, 32, 0 },
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{ "fixup_Mips_REL32", 0, 32, 0 },
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{ "fixup_Mips_26", 6, 26, 0 },
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{ "fixup_Mips_HI16", 16, 16, 0 },
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{ "fixup_Mips_LO16", 16, 16, 0 },
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{ "fixup_Mips_GPREL16", 16, 16, 0 },
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{ "fixup_Mips_LITERAL", 16, 16, 0 },
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{ "fixup_Mips_GOT_Global", 16, 16, 0 },
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{ "fixup_Mips_GOT_Local", 16, 16, 0 },
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{ "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_Mips_CALL16", 16, 16, 0 },
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{ "fixup_Mips_GPREL32", 0, 32, 0 },
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{ "fixup_Mips_SHIFT5", 21, 5, 0 },
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{ "fixup_Mips_SHIFT6", 21, 5, 0 },
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{ "fixup_Mips_64", 0, 64, 0 },
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{ "fixup_Mips_TLSGD", 16, 16, 0 },
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{ "fixup_Mips_GOTTPREL", 16, 16, 0 },
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{ "fixup_Mips_TPREL_HI", 16, 16, 0 },
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{ "fixup_Mips_TPREL_LO", 16, 16, 0 },
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{ "fixup_Mips_TLSLDM", 16, 16, 0 },
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{ "fixup_Mips_DTPREL_HI", 16, 16, 0 },
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{ "fixup_Mips_DTPREL_LO", 16, 16, 0 },
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{ "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_Mips_GPOFF_HI", 16, 16, 0 },
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{ "fixup_Mips_GPOFF_LO", 16, 16, 0 },
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{ "fixup_Mips_GOT_PAGE", 16, 16, 0 },
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{ "fixup_Mips_GOT_OFST", 16, 16, 0 },
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{ "fixup_Mips_GOT_DISP", 16, 16, 0 },
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{ "fixup_Mips_HIGHER", 16, 16, 0 },
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{ "fixup_Mips_HIGHEST", 16, 16, 0 },
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{ "fixup_Mips_GOT_HI16", 16, 16, 0 },
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{ "fixup_Mips_GOT_LO16", 16, 16, 0 },
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{ "fixup_Mips_CALL_HI16", 16, 16, 0 },
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{ "fixup_Mips_CALL_LO16", 16, 16, 0 },
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{ "fixup_MICROMIPS_26_S1", 6, 26, 0 },
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{ "fixup_MICROMIPS_HI16", 16, 16, 0 },
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{ "fixup_MICROMIPS_LO16", 16, 16, 0 },
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{ "fixup_MICROMIPS_GOT16", 16, 16, 0 },
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{ "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_MICROMIPS_CALL16", 16, 16, 0 },
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{ "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 },
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{ "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 },
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{ "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 },
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{ "fixup_MICROMIPS_TLS_GD", 16, 16, 0 },
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{ "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 },
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{ "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 },
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{ "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 },
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{ "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 },
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{ "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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if (IsLittle)
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return LittleEndianInfos[Kind - FirstTargetFixupKind];
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return BigEndianInfos[Kind - FirstTargetFixupKind];
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}
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/// WriteNopData - Write an (optimal) nop sequence of Count bytes
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/// to the given output. If the target cannot generate such a sequence,
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/// it should return an error.
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///
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/// \return - True on success.
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bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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// Check for a less than instruction size number of bytes
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// FIXME: 16 bit instructions are not handled yet here.
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// We shouldn't be using a hard coded number for instruction size.
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if (Count % 4) return false;
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uint64_t NumNops = Count / 4;
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for (uint64_t i = 0; i != NumNops; ++i)
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OW->Write32(0);
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return true;
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}
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/// processFixupValue - Target hook to process the literal value of a fixup
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/// if necessary.
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void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
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const MCAsmLayout &Layout,
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const MCFixup &Fixup,
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const MCFragment *DF,
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const MCValue &Target,
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uint64_t &Value,
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bool &IsResolved) {
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// At this point we'll ignore the value returned by adjustFixupValue as
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// we are only checking if the fixup can be applied correctly. We have
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// access to MCContext from here which allows us to report a fatal error
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// with *possibly* a source code location.
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(void)adjustFixupValue(Fixup, Value, &Asm.getContext());
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}
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// MCAsmBackend
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MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
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const MCRegisterInfo &MRI,
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StringRef TT,
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StringRef CPU) {
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return new MipsAsmBackend(T, Triple(TT).getOS(),
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/*IsLittle*/true, /*Is64Bit*/false);
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}
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MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
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const MCRegisterInfo &MRI,
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StringRef TT,
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StringRef CPU) {
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return new MipsAsmBackend(T, Triple(TT).getOS(),
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/*IsLittle*/false, /*Is64Bit*/false);
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}
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MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
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const MCRegisterInfo &MRI,
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StringRef TT,
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StringRef CPU) {
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return new MipsAsmBackend(T, Triple(TT).getOS(),
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/*IsLittle*/true, /*Is64Bit*/true);
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}
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MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
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const MCRegisterInfo &MRI,
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StringRef TT,
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StringRef CPU) {
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return new MipsAsmBackend(T, Triple(TT).getOS(),
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/*IsLittle*/false, /*Is64Bit*/true);
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}
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