llvm-6502/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll
Juergen Ributzka 7440a83e60 Reapply "[FastISel][AArch64] Add custom lowering for GEPs."
This is mostly a copy of the existing FastISel GEP code, but we have to
duplicate it for AArch64, because otherwise we would bail out even for simple
cases. This is because the standard fastEmit functions don't cover MUL at all
and ADD is lowered very inefficientily.

The original commit had a bug in the add emit logic, which has been fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219831 91177308-0d34-0410-b5e6-96231b3b80d8
2014-10-15 18:58:07 +00:00

25 lines
708 B
LLVM

; This test should cause the TargetMaterializeAlloca to be invoked
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
%struct.S1Ty = type { i64 }
%struct.S2Ty = type { %struct.S1Ty, %struct.S1Ty }
define void @takeS1(%struct.S1Ty* %V) nounwind {
entry:
%V.addr = alloca %struct.S1Ty*, align 8
store %struct.S1Ty* %V, %struct.S1Ty** %V.addr, align 8
ret void
}
define void @main() nounwind {
entry:
; CHECK: main
; CHECK: mov x29, sp
; CHECK: mov [[REG:x[0-9]+]], sp
; CHECK-NEXT: add x0, [[REG]], #8
%E = alloca %struct.S2Ty, align 4
%B = getelementptr inbounds %struct.S2Ty* %E, i32 0, i32 1
call void @takeS1(%struct.S1Ty* %B)
ret void
}