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https://github.com/c64scene-ar/llvm-6502.git
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add7c56be5
The generic FastISel code would bail, because it can't emit a sign-extend for AArch64. This copies the code over and uses AArch64 specific emit functions. This is not ideal and 'computeAddress' should handles this, so it can fold the address computation into the memory operation. I plan to clean up 'computeAddress' anyways, so I will add that in a future commit. Related to rdar://problem/18962471. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221923 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
1.3 KiB
LLVM
50 lines
1.3 KiB
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
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%struct.foo = type { i32, i64, float, double }
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define double* @test_struct(%struct.foo* %f) {
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; CHECK-LABEL: test_struct
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; CHECK: add x0, x0, #24
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%1 = getelementptr inbounds %struct.foo* %f, i64 0, i32 3
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ret double* %1
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}
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define i32* @test_array1(i32* %a, i64 %i) {
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; CHECK-LABEL: test_array1
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; CHECK: orr [[REG:x[0-9]+]], xzr, #0x4
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; CHECK-NEXT: madd x0, x1, [[REG]], x0
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%1 = getelementptr inbounds i32* %a, i64 %i
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ret i32* %1
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}
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define i32* @test_array2(i32* %a) {
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; CHECK-LABEL: test_array2
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; CHECK: add x0, x0, #16
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%1 = getelementptr inbounds i32* %a, i64 4
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ret i32* %1
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}
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define i32* @test_array3(i32* %a) {
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; CHECK-LABEL: test_array3
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; CHECK: add x0, x0, #1, lsl #12
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%1 = getelementptr inbounds i32* %a, i64 1024
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ret i32* %1
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}
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define i32* @test_array4(i32* %a) {
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; CHECK-LABEL: test_array4
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; CHECK: movz [[REG:x[0-9]+]], #0x1008
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; CHECK-NEXR: add x0, x0, [[REG]]
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%1 = getelementptr inbounds i32* %a, i64 1026
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ret i32* %1
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}
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define i32* @test_array5(i32* %a, i32 %i) {
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; CHECK-LABEL: test_array5
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; CHECK: sxtw [[REG1:x[0-9]+]], w1
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; CHECK-NEXT: orr [[REG2:x[0-9]+]], xzr, #0x4
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; CHECK-NEXT: madd {{x[0-9]+}}, [[REG1]], [[REG2]], x0
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%1 = getelementptr inbounds i32* %a, i32 %i
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ret i32* %1
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}
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