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https://github.com/c64scene-ar/llvm-6502.git
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5d6365c80c
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216225 91177308-0d34-0410-b5e6-96231b3b80d8
30 lines
854 B
LLVM
30 lines
854 B
LLVM
; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
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define i8* @test_frameaddress0() nounwind {
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entry:
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; CHECK-LABEL: test_frameaddress0:
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; CHECK: stp x29, x30, [sp, #-16]!
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; CHECK: mov x29, sp
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; CHECK: mov x0, x29
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; CHECK: ldp x29, x30, [sp], #16
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; CHECK: ret
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%0 = call i8* @llvm.frameaddress(i32 0)
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ret i8* %0
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}
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define i8* @test_frameaddress2() nounwind {
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entry:
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; CHECK-LABEL: test_frameaddress2:
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; CHECK: stp x29, x30, [sp, #-16]!
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; CHECK: mov x29, sp
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; CHECK: ldr x[[reg:[0-9]+]], [x29]
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; CHECK: ldr x0, [x[[reg]]]
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; CHECK: ldp x29, x30, [sp], #16
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; CHECK: ret
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%0 = call i8* @llvm.frameaddress(i32 2)
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ret i8* %0
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}
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declare i8* @llvm.frameaddress(i32) nounwind readnone
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