mirror of
https://github.com/c64scene-ar/llvm-6502.git
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29f94c7201
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209577 91177308-0d34-0410-b5e6-96231b3b80d8
225 lines
7.9 KiB
LLVM
225 lines
7.9 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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@var1_32 = global i32 0
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@var2_32 = global i32 0
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@var1_64 = global i64 0
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@var2_64 = global i64 0
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define void @logical_32bit() minsize {
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; CHECK-LABEL: logical_32bit:
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%val1 = load i32* @var1_32
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%val2 = load i32* @var2_32
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; First check basic and/bic/or/orn/eor/eon patterns with no shift
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%neg_val2 = xor i32 -1, %val2
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%and_noshift = and i32 %val1, %val2
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; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %and_noshift, i32* @var1_32
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%bic_noshift = and i32 %neg_val2, %val1
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; CHECK: bic {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %bic_noshift, i32* @var1_32
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%or_noshift = or i32 %val1, %val2
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; CHECK: orr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %or_noshift, i32* @var1_32
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%orn_noshift = or i32 %neg_val2, %val1
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; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %orn_noshift, i32* @var1_32
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%xor_noshift = xor i32 %val1, %val2
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; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %xor_noshift, i32* @var1_32
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%xorn_noshift = xor i32 %neg_val2, %val1
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; CHECK: eon {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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store volatile i32 %xorn_noshift, i32* @var1_32
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; Check the maximum shift on each
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%operand_lsl31 = shl i32 %val2, 31
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%neg_operand_lsl31 = xor i32 -1, %operand_lsl31
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%and_lsl31 = and i32 %val1, %operand_lsl31
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; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
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store volatile i32 %and_lsl31, i32* @var1_32
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%bic_lsl31 = and i32 %val1, %neg_operand_lsl31
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; CHECK: bic {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
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store volatile i32 %bic_lsl31, i32* @var1_32
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%or_lsl31 = or i32 %val1, %operand_lsl31
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; CHECK: orr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
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store volatile i32 %or_lsl31, i32* @var1_32
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%orn_lsl31 = or i32 %val1, %neg_operand_lsl31
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; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
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store volatile i32 %orn_lsl31, i32* @var1_32
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%xor_lsl31 = xor i32 %val1, %operand_lsl31
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; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
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store volatile i32 %xor_lsl31, i32* @var1_32
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%xorn_lsl31 = xor i32 %val1, %neg_operand_lsl31
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; CHECK: eon {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
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store volatile i32 %xorn_lsl31, i32* @var1_32
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; Check other shifts on a subset
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%operand_asr10 = ashr i32 %val2, 10
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%neg_operand_asr10 = xor i32 -1, %operand_asr10
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%bic_asr10 = and i32 %val1, %neg_operand_asr10
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; CHECK: bic {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #10
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store volatile i32 %bic_asr10, i32* @var1_32
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%xor_asr10 = xor i32 %val1, %operand_asr10
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; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #10
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store volatile i32 %xor_asr10, i32* @var1_32
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%operand_lsr1 = lshr i32 %val2, 1
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%neg_operand_lsr1 = xor i32 -1, %operand_lsr1
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%orn_lsr1 = or i32 %val1, %neg_operand_lsr1
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; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #1
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store volatile i32 %orn_lsr1, i32* @var1_32
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%xor_lsr1 = xor i32 %val1, %operand_lsr1
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; CHECK: eor {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #1
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store volatile i32 %xor_lsr1, i32* @var1_32
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%operand_ror20_big = shl i32 %val2, 12
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%operand_ror20_small = lshr i32 %val2, 20
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%operand_ror20 = or i32 %operand_ror20_big, %operand_ror20_small
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%neg_operand_ror20 = xor i32 -1, %operand_ror20
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%xorn_ror20 = xor i32 %val1, %neg_operand_ror20
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; CHECK: eon {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, ror #20
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store volatile i32 %xorn_ror20, i32* @var1_32
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%and_ror20 = and i32 %val1, %operand_ror20
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; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, ror #20
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store volatile i32 %and_ror20, i32* @var1_32
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ret void
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}
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define void @logical_64bit() minsize {
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; CHECK-LABEL: logical_64bit:
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%val1 = load i64* @var1_64
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%val2 = load i64* @var2_64
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; First check basic and/bic/or/orn/eor/eon patterns with no shift
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%neg_val2 = xor i64 -1, %val2
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%and_noshift = and i64 %val1, %val2
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; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %and_noshift, i64* @var1_64
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%bic_noshift = and i64 %neg_val2, %val1
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; CHECK: bic {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %bic_noshift, i64* @var1_64
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%or_noshift = or i64 %val1, %val2
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; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %or_noshift, i64* @var1_64
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%orn_noshift = or i64 %neg_val2, %val1
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; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %orn_noshift, i64* @var1_64
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%xor_noshift = xor i64 %val1, %val2
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; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %xor_noshift, i64* @var1_64
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%xorn_noshift = xor i64 %neg_val2, %val1
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; CHECK: eon {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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store volatile i64 %xorn_noshift, i64* @var1_64
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; Check the maximum shift on each
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%operand_lsl63 = shl i64 %val2, 63
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%neg_operand_lsl63 = xor i64 -1, %operand_lsl63
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%and_lsl63 = and i64 %val1, %operand_lsl63
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; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
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store volatile i64 %and_lsl63, i64* @var1_64
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%bic_lsl63 = and i64 %val1, %neg_operand_lsl63
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; CHECK: bic {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
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store volatile i64 %bic_lsl63, i64* @var1_64
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%or_lsl63 = or i64 %val1, %operand_lsl63
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; CHECK: orr {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
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store volatile i64 %or_lsl63, i64* @var1_64
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%orn_lsl63 = or i64 %val1, %neg_operand_lsl63
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; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
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store volatile i64 %orn_lsl63, i64* @var1_64
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%xor_lsl63 = xor i64 %val1, %operand_lsl63
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; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
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store volatile i64 %xor_lsl63, i64* @var1_64
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%xorn_lsl63 = xor i64 %val1, %neg_operand_lsl63
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; CHECK: eon {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
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store volatile i64 %xorn_lsl63, i64* @var1_64
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; Check other shifts on a subset
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%operand_asr10 = ashr i64 %val2, 10
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%neg_operand_asr10 = xor i64 -1, %operand_asr10
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%bic_asr10 = and i64 %val1, %neg_operand_asr10
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; CHECK: bic {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #10
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store volatile i64 %bic_asr10, i64* @var1_64
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%xor_asr10 = xor i64 %val1, %operand_asr10
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; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #10
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store volatile i64 %xor_asr10, i64* @var1_64
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%operand_lsr1 = lshr i64 %val2, 1
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%neg_operand_lsr1 = xor i64 -1, %operand_lsr1
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%orn_lsr1 = or i64 %val1, %neg_operand_lsr1
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; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #1
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store volatile i64 %orn_lsr1, i64* @var1_64
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%xor_lsr1 = xor i64 %val1, %operand_lsr1
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; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #1
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store volatile i64 %xor_lsr1, i64* @var1_64
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; Construct a rotate-right from a bunch of other logical
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; operations. DAGCombiner should ensure we the ROTR during
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; selection
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%operand_ror20_big = shl i64 %val2, 44
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%operand_ror20_small = lshr i64 %val2, 20
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%operand_ror20 = or i64 %operand_ror20_big, %operand_ror20_small
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%neg_operand_ror20 = xor i64 -1, %operand_ror20
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%xorn_ror20 = xor i64 %val1, %neg_operand_ror20
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; CHECK: eon {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, ror #20
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store volatile i64 %xorn_ror20, i64* @var1_64
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%and_ror20 = and i64 %val1, %operand_ror20
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; CHECK: and {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, ror #20
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store volatile i64 %and_ror20, i64* @var1_64
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ret void
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}
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define void @flag_setting() {
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; CHECK-LABEL: flag_setting:
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%val1 = load i64* @var1_64
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%val2 = load i64* @var2_64
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; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}
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; CHECK: b.gt .L
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%simple_and = and i64 %val1, %val2
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%tst1 = icmp sgt i64 %simple_and, 0
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br i1 %tst1, label %ret, label %test2
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test2:
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; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
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; CHECK: b.lt .L
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%shifted_op = shl i64 %val2, 63
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%shifted_and = and i64 %val1, %shifted_op
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%tst2 = icmp slt i64 %shifted_and, 0
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br i1 %tst2, label %ret, label %test3
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test3:
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; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}, asr #12
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; CHECK: b.gt .L
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%asr_op = ashr i64 %val2, 12
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%asr_and = and i64 %asr_op, %val1
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%tst3 = icmp sgt i64 %asr_and, 0
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br i1 %tst3, label %ret, label %other_exit
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other_exit:
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store volatile i64 %val1, i64* @var1_64
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ret void
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ret:
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ret void
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}
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