Hal Finkel b45eb9fd27 PPCInstrInfo::optimizeCompareInstr should not optimize FP compares ...

The floating-point record forms on PPC don't set the condition register bits
based on a comparison with zero (like the integer record forms do), but rather
based on the exception status bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181423 91177308-0d34-0410-b5e6-96231b3b80d8

2013-05-08 12:16:14 +00:00

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AArch64

AArch64: support literal pool access in large memory model.

2013-05-04 16:54:07 +00:00

ARM

Test case for r181160 and r181161. rdar://13782395

2013-05-05 18:07:15 +00:00

CPP

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Generic

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Hexagon

Hexagon: Fix Small Data support to handle -G 0 correctly.

2013-05-07 19:53:00 +00:00

Inputs

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MBlaze

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Mips

Remove some uneeded pseudos in the presence of the naked function attribute.

2013-05-03 23:17:24 +00:00

MSP430

DAGCombiner: Simplify inverted bit tests

2013-05-08 06:44:42 +00:00

NVPTX

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PowerPC

PPCInstrInfo::optimizeCompareInstr should not optimize FP compares

2013-05-08 12:16:14 +00:00

R600

R600: Emit config values in register / value pairs

2013-05-06 17:50:51 +00:00

SI

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SPARC

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SystemZ

[SystemZ] Add CodeGen test cases

2013-05-06 16:17:29 +00:00

Thumb

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Thumb2

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X86

Fix a bug in codegenprep where it was losing track of values OptimizeMemoryInst

2013-05-08 09:00:10 +00:00

XCore

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