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b4691b495d
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191514 91177308-0d34-0410-b5e6-96231b3b80d8
138 lines
4.0 KiB
LLVM
138 lines
4.0 KiB
LLVM
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
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@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
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@v2f64 = global <2 x double> <double 0.0, double 0.0>
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define void @const_v4f32() nounwind {
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; MIPS32: const_v4f32:
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store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
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; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
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store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
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; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
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store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
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; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
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store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
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; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
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store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
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; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
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store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
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; MIPS32: ld.w [[R1:\$w[0-9]+]], %lo(
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ret void
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; MIPS32: .size const_v4f32
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}
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define void @const_v2f64() nounwind {
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; MIPS32: const_v2f64:
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store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
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; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
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store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
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; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
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store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
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; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
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store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
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; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
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store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
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; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
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store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
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; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
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store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
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; MIPS32: ld.d [[R1:\$w[0-9]+]], %lo(
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ret void
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; MIPS32: .size const_v2f64
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}
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define float @extract_v4f32() nounwind {
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; MIPS32: extract_v4f32:
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%1 = load <4 x float>* @v4f32
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; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
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%2 = fadd <4 x float> %1, %1
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; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = extractelement <4 x float> %2, i32 1
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; Element 1 can be obtained by splatting it across the vector and extracting
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; $w0:sub_lo
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; MIPS32-DAG: splati.w $w0, [[R1]][1]
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ret float %3
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; MIPS32: .size extract_v4f32
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}
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define float @extract_v4f32_elt0() nounwind {
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; MIPS32: extract_v4f32_elt0:
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%1 = load <4 x float>* @v4f32
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; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
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%2 = fadd <4 x float> %1, %1
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; MIPS32-DAG: fadd.w $w0, [[R1]], [[R1]]
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%3 = extractelement <4 x float> %2, i32 0
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; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
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; MIPS32-NOT: copy_u.w
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; MIPS32-NOT: mtc1
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ret float %3
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; MIPS32: .size extract_v4f32_elt0
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}
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define double @extract_v2f64() nounwind {
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; MIPS32: extract_v2f64:
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%1 = load <2 x double>* @v2f64
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; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
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%2 = fadd <2 x double> %1, %1
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; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = extractelement <2 x double> %2, i32 1
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; Element 1 can be obtained by splatting it across the vector and extracting
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; $w0:sub_64
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; MIPS32-DAG: splati.d $w0, [[R1]][1]
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; MIPS32-NOT: copy_u.w
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; MIPS32-NOT: mtc1
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; MIPS32-NOT: mthc1
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; MIPS32-NOT: sll
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; MIPS32-NOT: sra
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ret double %3
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; MIPS32: .size extract_v2f64
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}
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define double @extract_v2f64_elt0() nounwind {
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; MIPS32: extract_v2f64_elt0:
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%1 = load <2 x double>* @v2f64
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; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
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%2 = fadd <2 x double> %1, %1
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; MIPS32-DAG: fadd.d $w0, [[R1]], [[R1]]
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%3 = extractelement <2 x double> %2, i32 0
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; Element 0 can be obtained by extracting $w0:sub_64 ($f0)
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; MIPS32-NOT: copy_u.w
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; MIPS32-NOT: mtc1
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; MIPS32-NOT: mthc1
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; MIPS32-NOT: sll
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; MIPS32-NOT: sra
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ret double %3
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; MIPS32: .size extract_v2f64_elt0
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}
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