mirror of
https://github.com/c64scene-ar/llvm-6502.git
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120ab480ab
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23531 91177308-0d34-0410-b5e6-96231b3b80d8
1906 lines
66 KiB
C++
1906 lines
66 KiB
C++
//===- AlphaISelPattern.cpp - A pattern matching inst selector for Alpha --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for Alpha.
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//
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//===----------------------------------------------------------------------===//
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#include "Alpha.h"
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#include "AlphaRegisterInfo.h"
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#include "AlphaTargetMachine.h"
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#include "AlphaISelLowering.h"
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#include "llvm/Constants.h" // FIXME: REMOVE
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#include "llvm/Function.h"
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#include "llvm/Module.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/CommandLine.h"
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#include <set>
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#include <algorithm>
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using namespace llvm;
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namespace llvm {
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cl::opt<bool> EnableAlphaIDIV("enable-alpha-intfpdiv",
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cl::desc("Use the FP div instruction for integer div when possible"),
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cl::Hidden);
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cl::opt<bool> EnableAlphaCount("enable-alpha-count",
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cl::desc("Print estimates on live ins and outs"),
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cl::Hidden);
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cl::opt<bool> EnableAlphaLSMark("enable-alpha-lsmark",
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cl::desc("Emit symbols to correlate Mem ops to LLVM Values"),
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cl::Hidden);
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}
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namespace {
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//===--------------------------------------------------------------------===//
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/// ISel - Alpha specific code to select Alpha machine instructions for
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/// SelectionDAG operations.
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//===--------------------------------------------------------------------===//
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class AlphaISel : public SelectionDAGISel {
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/// AlphaLowering - This object fully describes how to lower LLVM code to an
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/// Alpha-specific SelectionDAG.
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AlphaTargetLowering AlphaLowering;
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SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform
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// for sdiv and udiv until it is put into the future
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// dag combiner.
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/// ExprMap - As shared expressions are codegen'd, we keep track of which
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/// vreg the value is produced in, so we only emit one copy of each compiled
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/// tree.
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static const unsigned notIn = (unsigned)(-1);
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std::map<SDOperand, unsigned> ExprMap;
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//CCInvMap sometimes (SetNE) we have the inverse CC code for free
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std::map<SDOperand, unsigned> CCInvMap;
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int count_ins;
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int count_outs;
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bool has_sym;
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int max_depth;
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public:
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AlphaISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering),
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AlphaLowering(TM)
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{}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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count_ins = 0;
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count_outs = 0;
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max_depth = 0;
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has_sym = false;
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// Codegen the basic block.
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ISelDAG = &DAG;
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max_depth = DAG.getRoot().getNodeDepth();
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Select(DAG.getRoot());
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if(has_sym)
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++count_ins;
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if(EnableAlphaCount)
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std::cerr << "COUNT: "
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<< BB->getParent()->getFunction ()->getName() << " "
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<< BB->getNumber() << " "
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<< max_depth << " "
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<< count_ins << " "
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<< count_outs << "\n";
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// Clear state used for selection.
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ExprMap.clear();
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CCInvMap.clear();
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}
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unsigned SelectExpr(SDOperand N);
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void Select(SDOperand N);
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void SelectAddr(SDOperand N, unsigned& Reg, long& offset);
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void SelectBranchCC(SDOperand N);
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void MoveFP2Int(unsigned src, unsigned dst, bool isDouble);
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void MoveInt2FP(unsigned src, unsigned dst, bool isDouble);
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//returns whether the sense of the comparison was inverted
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bool SelectFPSetCC(SDOperand N, unsigned dst);
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// dag -> dag expanders for integer divide by constant
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SDOperand BuildSDIVSequence(SDOperand N);
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SDOperand BuildUDIVSequence(SDOperand N);
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};
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}
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static bool isSIntImmediate(SDOperand N, int64_t& Imm) {
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// test for constant
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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// retrieve value
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Imm = CN->getSignExtended();
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// passes muster
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return true;
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}
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// not a constant
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return false;
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}
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// isSIntImmediateBounded - This method tests to see if a constant operand
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// bounded s.t. low <= Imm <= high
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// If so Imm will receive the 64 bit value.
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static bool isSIntImmediateBounded(SDOperand N, int64_t& Imm,
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int64_t low, int64_t high) {
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if (isSIntImmediate(N, Imm) && Imm <= high && Imm >= low)
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return true;
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return false;
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}
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static bool isUIntImmediate(SDOperand N, uint64_t& Imm) {
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// test for constant
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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// retrieve value
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Imm = (uint64_t)CN->getValue();
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// passes muster
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return true;
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}
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// not a constant
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return false;
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}
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static bool isUIntImmediateBounded(SDOperand N, uint64_t& Imm,
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uint64_t low, uint64_t high) {
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if (isUIntImmediate(N, Imm) && Imm <= high && Imm >= low)
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return true;
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return false;
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}
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static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
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{
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fun = type = offset = 0;
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if (v == NULL) {
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type = 0;
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} else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) {
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type = 1;
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const Module* M = GV->getParent();
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for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii)
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++offset;
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} else if (const Argument* Arg = dyn_cast<Argument>(v)) {
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type = 2;
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const Function* F = Arg->getParent();
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const Module* M = F->getParent();
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for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
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++fun;
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for(Function::const_arg_iterator ii = F->arg_begin(); &*ii != Arg; ++ii)
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++offset;
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} else if (const Instruction* I = dyn_cast<Instruction>(v)) {
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assert(dyn_cast<PointerType>(I->getType()));
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type = 3;
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const BasicBlock* bb = I->getParent();
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const Function* F = bb->getParent();
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const Module* M = F->getParent();
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for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
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++fun;
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for(Function::const_iterator ii = F->begin(); &*ii != bb; ++ii)
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offset += ii->size();
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for(BasicBlock::const_iterator ii = bb->begin(); &*ii != I; ++ii)
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++offset;
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} else if (const Constant* C = dyn_cast<Constant>(v)) {
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//Don't know how to look these up yet
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type = 0;
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} else {
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assert(0 && "Error in value marking");
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}
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//type = 4: register spilling
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//type = 5: global address loading or constant loading
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}
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static int getUID()
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{
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static int id = 0;
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return ++id;
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}
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//Factorize a number using the list of constants
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static bool factorize(int v[], int res[], int size, uint64_t c)
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{
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bool cont = true;
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while (c != 1 && cont)
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{
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cont = false;
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for(int i = 0; i < size; ++i)
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{
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if (c % v[i] == 0)
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{
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c /= v[i];
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++res[i];
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cont=true;
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}
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}
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}
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return c == 1;
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}
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//Shamelessly adapted from PPC32
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// Structure used to return the necessary information to codegen an SDIV as
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// a multiply.
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struct ms {
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int64_t m; // magic number
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int64_t s; // shift amount
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};
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struct mu {
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uint64_t m; // magic number
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int64_t a; // add indicator
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int64_t s; // shift amount
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};
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/// magic - calculate the magic numbers required to codegen an integer sdiv as
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/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
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/// or -1.
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static struct ms magic(int64_t d) {
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int64_t p;
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uint64_t ad, anc, delta, q1, r1, q2, r2, t;
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const uint64_t two63 = 9223372036854775808ULL; // 2^63
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struct ms mag;
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ad = llabs(d);
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t = two63 + ((uint64_t)d >> 63);
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anc = t - 1 - t%ad; // absolute value of nc
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p = 63; // initialize p
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q1 = two63/anc; // initialize q1 = 2p/abs(nc)
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r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
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q2 = two63/ad; // initialize q2 = 2p/abs(d)
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r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
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do {
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p = p + 1;
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q1 = 2*q1; // update q1 = 2p/abs(nc)
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r1 = 2*r1; // update r1 = rem(2p/abs(nc))
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if (r1 >= anc) { // must be unsigned comparison
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q1 = q1 + 1;
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r1 = r1 - anc;
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}
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q2 = 2*q2; // update q2 = 2p/abs(d)
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r2 = 2*r2; // update r2 = rem(2p/abs(d))
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if (r2 >= ad) { // must be unsigned comparison
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q2 = q2 + 1;
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r2 = r2 - ad;
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}
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delta = ad - r2;
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} while (q1 < delta || (q1 == delta && r1 == 0));
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mag.m = q2 + 1;
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if (d < 0) mag.m = -mag.m; // resulting magic number
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mag.s = p - 64; // resulting shift
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return mag;
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}
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/// magicu - calculate the magic numbers required to codegen an integer udiv as
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/// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
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static struct mu magicu(uint64_t d)
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{
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int64_t p;
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uint64_t nc, delta, q1, r1, q2, r2;
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struct mu magu;
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magu.a = 0; // initialize "add" indicator
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nc = - 1 - (-d)%d;
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p = 63; // initialize p
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q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
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r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
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q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
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r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
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do {
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p = p + 1;
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if (r1 >= nc - r1 ) {
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q1 = 2*q1 + 1; // update q1
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r1 = 2*r1 - nc; // update r1
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}
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else {
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q1 = 2*q1; // update q1
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r1 = 2*r1; // update r1
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}
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if (r2 + 1 >= d - r2) {
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if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
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q2 = 2*q2 + 1; // update q2
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r2 = 2*r2 + 1 - d; // update r2
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}
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else {
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if (q2 >= 0x8000000000000000ull) magu.a = 1;
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q2 = 2*q2; // update q2
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r2 = 2*r2 + 1; // update r2
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}
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delta = d - 1 - r2;
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} while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
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magu.m = q2 + 1; // resulting magic number
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magu.s = p - 64; // resulting shift
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return magu;
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}
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/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
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/// return a DAG expression to select that will generate the same value by
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/// multiplying by a magic number. See:
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/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
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SDOperand AlphaISel::BuildSDIVSequence(SDOperand N) {
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int64_t d = (int64_t)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
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ms magics = magic(d);
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// Multiply the numerator (operand 0) by the magic value
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SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i64, N.getOperand(0),
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ISelDAG->getConstant(magics.m, MVT::i64));
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// If d > 0 and m < 0, add the numerator
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if (d > 0 && magics.m < 0)
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Q = ISelDAG->getNode(ISD::ADD, MVT::i64, Q, N.getOperand(0));
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// If d < 0 and m > 0, subtract the numerator.
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if (d < 0 && magics.m > 0)
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Q = ISelDAG->getNode(ISD::SUB, MVT::i64, Q, N.getOperand(0));
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// Shift right algebraic if shift value is nonzero
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if (magics.s > 0)
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Q = ISelDAG->getNode(ISD::SRA, MVT::i64, Q,
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ISelDAG->getConstant(magics.s, MVT::i64));
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// Extract the sign bit and add it to the quotient
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SDOperand T =
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ISelDAG->getNode(ISD::SRL, MVT::i64, Q, ISelDAG->getConstant(63, MVT::i64));
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return ISelDAG->getNode(ISD::ADD, MVT::i64, Q, T);
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}
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/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
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/// return a DAG expression to select that will generate the same value by
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/// multiplying by a magic number. See:
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/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
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SDOperand AlphaISel::BuildUDIVSequence(SDOperand N) {
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unsigned d =
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(unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
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mu magics = magicu(d);
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// Multiply the numerator (operand 0) by the magic value
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SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i64, N.getOperand(0),
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ISelDAG->getConstant(magics.m, MVT::i64));
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if (magics.a == 0) {
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Q = ISelDAG->getNode(ISD::SRL, MVT::i64, Q,
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ISelDAG->getConstant(magics.s, MVT::i64));
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} else {
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SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i64, N.getOperand(0), Q);
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NPQ = ISelDAG->getNode(ISD::SRL, MVT::i64, NPQ,
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ISelDAG->getConstant(1, MVT::i64));
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NPQ = ISelDAG->getNode(ISD::ADD, MVT::i64, NPQ, Q);
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Q = ISelDAG->getNode(ISD::SRL, MVT::i64, NPQ,
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ISelDAG->getConstant(magics.s-1, MVT::i64));
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}
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return Q;
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}
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//These describe LDAx
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static const int IMM_LOW = -32768;
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static const int IMM_HIGH = 32767;
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static const int IMM_MULT = 65536;
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static long getUpper16(long l)
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{
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long y = l / IMM_MULT;
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if (l % IMM_MULT > IMM_HIGH)
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++y;
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return y;
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}
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static long getLower16(long l)
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{
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long h = getUpper16(l);
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return l - h * IMM_MULT;
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}
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static unsigned GetRelVersion(unsigned opcode)
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{
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switch (opcode) {
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default: assert(0 && "unknown load or store"); return 0;
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case Alpha::LDQ: return Alpha::LDQr;
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case Alpha::LDS: return Alpha::LDSr;
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case Alpha::LDT: return Alpha::LDTr;
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case Alpha::LDL: return Alpha::LDLr;
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case Alpha::LDBU: return Alpha::LDBUr;
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case Alpha::LDWU: return Alpha::LDWUr;
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case Alpha::STB: return Alpha::STBr;
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case Alpha::STW: return Alpha::STWr;
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case Alpha::STL: return Alpha::STLr;
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case Alpha::STQ: return Alpha::STQr;
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case Alpha::STS: return Alpha::STSr;
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case Alpha::STT: return Alpha::STTr;
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}
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}
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void AlphaISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
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{
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unsigned Opc;
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if (TLI.getTargetMachine().getSubtarget<AlphaSubtarget>().hasF2I()) {
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Opc = isDouble ? Alpha::FTOIT : Alpha::FTOIS;
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BuildMI(BB, Opc, 1, dst).addReg(src).addReg(Alpha::F31);
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} else {
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//The hard way:
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// Spill the integer to memory and reload it from there.
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unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
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MachineFunction *F = BB->getParent();
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int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
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.addImm(getUID());
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Opc = isDouble ? Alpha::STT : Alpha::STS;
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BuildMI(BB, Opc, 3).addReg(src).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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if (EnableAlphaLSMark)
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BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
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.addImm(getUID());
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Opc = isDouble ? Alpha::LDQ : Alpha::LDL;
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BuildMI(BB, Alpha::LDQ, 2, dst).addFrameIndex(FrameIdx).addReg(Alpha::F31);
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}
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}
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void AlphaISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble)
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{
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unsigned Opc;
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if (TLI.getTargetMachine().getSubtarget<AlphaSubtarget>().hasF2I()) {
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Opc = isDouble?Alpha::ITOFT:Alpha::ITOFS;
|
|
BuildMI(BB, Opc, 1, dst).addReg(src).addReg(Alpha::R31);
|
|
} else {
|
|
//The hard way:
|
|
// Spill the integer to memory and reload it from there.
|
|
unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
|
|
MachineFunction *F = BB->getParent();
|
|
int FrameIdx = F->getFrameInfo()->CreateStackObject(Size, 8);
|
|
|
|
if (EnableAlphaLSMark)
|
|
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
|
|
.addImm(getUID());
|
|
Opc = isDouble ? Alpha::STQ : Alpha::STL;
|
|
BuildMI(BB, Opc, 3).addReg(src).addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
|
|
|
if (EnableAlphaLSMark)
|
|
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(0)
|
|
.addImm(getUID());
|
|
Opc = isDouble ? Alpha::LDT : Alpha::LDS;
|
|
BuildMI(BB, Opc, 2, dst).addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
|
}
|
|
}
|
|
|
|
bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst)
|
|
{
|
|
SDNode *SetCC = N.Val;
|
|
unsigned Opc, Tmp1, Tmp2, Tmp3;
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
|
|
bool rev = false;
|
|
bool inv = false;
|
|
|
|
switch (CC) {
|
|
default: SetCC->dump(); assert(0 && "Unknown FP comparison!");
|
|
case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
|
|
case ISD::SETLT: Opc = Alpha::CMPTLT; break;
|
|
case ISD::SETLE: Opc = Alpha::CMPTLE; break;
|
|
case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
|
|
case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
|
|
case ISD::SETNE: Opc = Alpha::CMPTEQ; inv = true; break;
|
|
}
|
|
|
|
ConstantFPSDNode *CN;
|
|
if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(0)))
|
|
&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
|
|
Tmp1 = Alpha::F31;
|
|
else
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
|
|
if ((CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
|
|
&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
|
|
Tmp2 = Alpha::F31;
|
|
else
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
|
|
//Can only compare doubles, and dag won't promote for me
|
|
if (SetCC->getOperand(0).getValueType() == MVT::f32)
|
|
{
|
|
//assert(0 && "Setcc On float?\n");
|
|
std::cerr << "Setcc on float!\n";
|
|
Tmp3 = MakeReg(MVT::f64);
|
|
BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp1);
|
|
Tmp1 = Tmp3;
|
|
}
|
|
if (SetCC->getOperand(1).getValueType() == MVT::f32)
|
|
{
|
|
//assert (0 && "Setcc On float?\n");
|
|
std::cerr << "Setcc on float!\n";
|
|
Tmp3 = MakeReg(MVT::f64);
|
|
BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp2);
|
|
Tmp2 = Tmp3;
|
|
}
|
|
|
|
if (rev) std::swap(Tmp1, Tmp2);
|
|
//do the comparison
|
|
BuildMI(BB, Opc, 2, dst).addReg(Tmp1).addReg(Tmp2);
|
|
return inv;
|
|
}
|
|
|
|
//Check to see if the load is a constant offset from a base register
|
|
void AlphaISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
|
|
{
|
|
unsigned opcode = N.getOpcode();
|
|
if (opcode == ISD::ADD && N.getOperand(1).getOpcode() == ISD::Constant &&
|
|
cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 32767)
|
|
{ //Normal imm add
|
|
Reg = SelectExpr(N.getOperand(0));
|
|
offset = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
|
return;
|
|
}
|
|
Reg = SelectExpr(N);
|
|
offset = 0;
|
|
return;
|
|
}
|
|
|
|
void AlphaISel::SelectBranchCC(SDOperand N)
|
|
{
|
|
assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
|
|
MachineBasicBlock *Dest =
|
|
cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
|
|
unsigned Opc = Alpha::WTF;
|
|
|
|
Select(N.getOperand(0)); //chain
|
|
SDOperand CC = N.getOperand(1);
|
|
|
|
if (CC.getOpcode() == ISD::SETCC)
|
|
{
|
|
ISD::CondCode cCode= cast<CondCodeSDNode>(CC.getOperand(2))->get();
|
|
if (MVT::isInteger(CC.getOperand(0).getValueType())) {
|
|
//Dropping the CC is only useful if we are comparing to 0
|
|
bool RightZero = CC.getOperand(1).getOpcode() == ISD::Constant &&
|
|
cast<ConstantSDNode>(CC.getOperand(1))->getValue() == 0;
|
|
bool isNE = false;
|
|
|
|
//Fix up CC
|
|
if(cCode == ISD::SETNE)
|
|
isNE = true;
|
|
|
|
if (RightZero) {
|
|
switch (cCode) {
|
|
default: CC.Val->dump(); assert(0 && "Unknown integer comparison!");
|
|
case ISD::SETEQ: Opc = Alpha::BEQ; break;
|
|
case ISD::SETLT: Opc = Alpha::BLT; break;
|
|
case ISD::SETLE: Opc = Alpha::BLE; break;
|
|
case ISD::SETGT: Opc = Alpha::BGT; break;
|
|
case ISD::SETGE: Opc = Alpha::BGE; break;
|
|
case ISD::SETULT: assert(0 && "x (unsigned) < 0 is never true"); break;
|
|
case ISD::SETUGT: Opc = Alpha::BNE; break;
|
|
//Technically you could have this CC
|
|
case ISD::SETULE: Opc = Alpha::BEQ; break;
|
|
case ISD::SETUGE: assert(0 && "x (unsgined >= 0 is always true"); break;
|
|
case ISD::SETNE: Opc = Alpha::BNE; break;
|
|
}
|
|
unsigned Tmp1 = SelectExpr(CC.getOperand(0)); //Cond
|
|
BuildMI(BB, Opc, 2).addReg(Tmp1).addMBB(Dest);
|
|
return;
|
|
} else {
|
|
unsigned Tmp1 = SelectExpr(CC);
|
|
if (isNE)
|
|
BuildMI(BB, Alpha::BEQ, 2).addReg(CCInvMap[CC]).addMBB(Dest);
|
|
else
|
|
BuildMI(BB, Alpha::BNE, 2).addReg(Tmp1).addMBB(Dest);
|
|
return;
|
|
}
|
|
} else { //FP
|
|
//Any comparison between 2 values should be codegened as an folded
|
|
//branch, as moving CC to the integer register is very expensive
|
|
//for a cmp b: c = a - b;
|
|
//a = b: c = 0
|
|
//a < b: c < 0
|
|
//a > b: c > 0
|
|
|
|
bool invTest = false;
|
|
unsigned Tmp3;
|
|
|
|
ConstantFPSDNode *CN;
|
|
if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(1)))
|
|
&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
|
|
Tmp3 = SelectExpr(CC.getOperand(0));
|
|
else if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(0)))
|
|
&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
|
|
{
|
|
Tmp3 = SelectExpr(CC.getOperand(1));
|
|
invTest = true;
|
|
}
|
|
else
|
|
{
|
|
unsigned Tmp1 = SelectExpr(CC.getOperand(0));
|
|
unsigned Tmp2 = SelectExpr(CC.getOperand(1));
|
|
bool isD = CC.getOperand(0).getValueType() == MVT::f64;
|
|
Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
|
|
BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
|
|
.addReg(Tmp1).addReg(Tmp2);
|
|
}
|
|
|
|
switch (cCode) {
|
|
default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
|
|
case ISD::SETEQ: Opc = invTest ? Alpha::FBNE : Alpha::FBEQ; break;
|
|
case ISD::SETLT: Opc = invTest ? Alpha::FBGT : Alpha::FBLT; break;
|
|
case ISD::SETLE: Opc = invTest ? Alpha::FBGE : Alpha::FBLE; break;
|
|
case ISD::SETGT: Opc = invTest ? Alpha::FBLT : Alpha::FBGT; break;
|
|
case ISD::SETGE: Opc = invTest ? Alpha::FBLE : Alpha::FBGE; break;
|
|
case ISD::SETNE: Opc = invTest ? Alpha::FBEQ : Alpha::FBNE; break;
|
|
}
|
|
BuildMI(BB, Opc, 2).addReg(Tmp3).addMBB(Dest);
|
|
return;
|
|
}
|
|
abort(); //Should never be reached
|
|
} else {
|
|
//Giveup and do the stupid thing
|
|
unsigned Tmp1 = SelectExpr(CC);
|
|
BuildMI(BB, Alpha::BNE, 2).addReg(Tmp1).addMBB(Dest);
|
|
return;
|
|
}
|
|
abort(); //Should never be reached
|
|
}
|
|
|
|
unsigned AlphaISel::SelectExpr(SDOperand N) {
|
|
unsigned Result;
|
|
unsigned Tmp1, Tmp2 = 0, Tmp3;
|
|
unsigned Opc = 0;
|
|
unsigned opcode = N.getOpcode();
|
|
int64_t SImm;
|
|
uint64_t UImm;
|
|
|
|
SDNode *Node = N.Val;
|
|
MVT::ValueType DestType = N.getValueType();
|
|
bool isFP = DestType == MVT::f64 || DestType == MVT::f32;
|
|
|
|
unsigned &Reg = ExprMap[N];
|
|
if (Reg) return Reg;
|
|
|
|
switch(N.getOpcode()) {
|
|
default:
|
|
Reg = Result = (N.getValueType() != MVT::Other) ?
|
|
MakeReg(N.getValueType()) : notIn;
|
|
break;
|
|
case ISD::AssertSext:
|
|
case ISD::AssertZext:
|
|
return Reg = SelectExpr(N.getOperand(0));
|
|
case ISD::CALL:
|
|
case ISD::TAILCALL:
|
|
// If this is a call instruction, make sure to prepare ALL of the result
|
|
// values as well as the chain.
|
|
if (Node->getNumValues() == 1)
|
|
Reg = Result = notIn; // Void call, just a chain.
|
|
else {
|
|
Result = MakeReg(Node->getValueType(0));
|
|
ExprMap[N.getValue(0)] = Result;
|
|
for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
|
|
ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
|
|
ExprMap[SDOperand(Node, Node->getNumValues()-1)] = notIn;
|
|
}
|
|
break;
|
|
}
|
|
|
|
switch (opcode) {
|
|
default:
|
|
Node->dump();
|
|
assert(0 && "Node not handled!\n");
|
|
|
|
case ISD::CTPOP:
|
|
case ISD::CTTZ:
|
|
case ISD::CTLZ:
|
|
Opc = opcode == ISD::CTPOP ? Alpha::CTPOP :
|
|
(opcode == ISD::CTTZ ? Alpha::CTTZ : Alpha::CTLZ);
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
BuildMI(BB, Opc, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
|
|
return Result;
|
|
|
|
case ISD::MULHU:
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Alpha::UMULH, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
return Result;
|
|
case ISD::MULHS:
|
|
{
|
|
//MULHU - Ra<63>*Rb - Rb<63>*Ra
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
Tmp3 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::UMULH, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
|
|
unsigned V1 = MakeReg(MVT::i64);
|
|
unsigned V2 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::CMOVGE, 3, V1).addReg(Tmp2).addReg(Alpha::R31)
|
|
.addReg(Tmp1);
|
|
BuildMI(BB, Alpha::CMOVGE, 3, V2).addReg(Tmp1).addReg(Alpha::R31)
|
|
.addReg(Tmp2);
|
|
unsigned IRes = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::SUBQ, 2, IRes).addReg(Tmp3).addReg(V1);
|
|
BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(IRes).addReg(V2);
|
|
return Result;
|
|
}
|
|
case ISD::UNDEF: {
|
|
BuildMI(BB, Alpha::IDEF, 0, Result);
|
|
return Result;
|
|
}
|
|
|
|
case ISD::DYNAMIC_STACKALLOC:
|
|
// Generate both result values.
|
|
if (Result != notIn)
|
|
ExprMap[N.getValue(1)] = notIn; // Generate the token
|
|
else
|
|
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
|
|
|
|
// FIXME: We are currently ignoring the requested alignment for handling
|
|
// greater than the stack alignment. This will need to be revisited at some
|
|
// point. Align = N.getOperand(2);
|
|
|
|
if (!isa<ConstantSDNode>(N.getOperand(2)) ||
|
|
cast<ConstantSDNode>(N.getOperand(2))->getValue() != 0) {
|
|
std::cerr << "Cannot allocate stack object with greater alignment than"
|
|
<< " the stack alignment yet!";
|
|
abort();
|
|
}
|
|
|
|
Select(N.getOperand(0));
|
|
if (isSIntImmediateBounded(N.getOperand(1), SImm, 0, 32767))
|
|
BuildMI(BB, Alpha::LDA, 2, Alpha::R30).addImm(-SImm).addReg(Alpha::R30);
|
|
else {
|
|
Tmp1 = SelectExpr(N.getOperand(1));
|
|
// Subtract size from stack pointer, thereby allocating some space.
|
|
BuildMI(BB, Alpha::SUBQ, 2, Alpha::R30).addReg(Alpha::R30).addReg(Tmp1);
|
|
}
|
|
|
|
// Put a pointer to the space into the result register, by copying the stack
|
|
// pointer.
|
|
BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R30).addReg(Alpha::R30);
|
|
return Result;
|
|
|
|
case ISD::ConstantPool:
|
|
Tmp1 = BB->getParent()->getConstantPool()->
|
|
getConstantPoolIndex(cast<ConstantPoolSDNode>(N)->get());
|
|
AlphaLowering.restoreGP(BB);
|
|
Tmp2 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::LDAHr, 2, Tmp2).addConstantPoolIndex(Tmp1)
|
|
.addReg(Alpha::R29);
|
|
BuildMI(BB, Alpha::LDAr, 2, Result).addConstantPoolIndex(Tmp1)
|
|
.addReg(Tmp2);
|
|
return Result;
|
|
|
|
case ISD::FrameIndex:
|
|
BuildMI(BB, Alpha::LDA, 2, Result)
|
|
.addFrameIndex(cast<FrameIndexSDNode>(N)->getIndex())
|
|
.addReg(Alpha::F31);
|
|
return Result;
|
|
|
|
case ISD::EXTLOAD:
|
|
case ISD::ZEXTLOAD:
|
|
case ISD::SEXTLOAD:
|
|
case ISD::LOAD:
|
|
{
|
|
// Make sure we generate both values.
|
|
if (Result != notIn)
|
|
ExprMap[N.getValue(1)] = notIn; // Generate the token
|
|
else
|
|
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
|
|
|
|
SDOperand Chain = N.getOperand(0);
|
|
SDOperand Address = N.getOperand(1);
|
|
Select(Chain);
|
|
|
|
bool fpext = true;
|
|
|
|
if (opcode == ISD::LOAD)
|
|
switch (Node->getValueType(0)) {
|
|
default: Node->dump(); assert(0 && "Bad load!");
|
|
case MVT::i64: Opc = Alpha::LDQ; break;
|
|
case MVT::f64: Opc = Alpha::LDT; break;
|
|
case MVT::f32: Opc = Alpha::LDS; break;
|
|
}
|
|
else
|
|
switch (cast<VTSDNode>(Node->getOperand(3))->getVT()) {
|
|
default: Node->dump(); assert(0 && "Bad sign extend!");
|
|
case MVT::i32: Opc = Alpha::LDL;
|
|
assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
|
|
case MVT::i16: Opc = Alpha::LDWU;
|
|
assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
|
|
case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
|
|
case MVT::i8: Opc = Alpha::LDBU;
|
|
assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
|
|
}
|
|
|
|
int i, j, k;
|
|
if (EnableAlphaLSMark)
|
|
getValueInfo(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue(),
|
|
i, j, k);
|
|
|
|
GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
|
|
if (GASD && !GASD->getGlobal()->isExternal()) {
|
|
Tmp1 = MakeReg(MVT::i64);
|
|
AlphaLowering.restoreGP(BB);
|
|
BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
|
|
.addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
|
|
if (EnableAlphaLSMark)
|
|
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
|
|
.addImm(getUID());
|
|
BuildMI(BB, GetRelVersion(Opc), 2, Result)
|
|
.addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
|
|
} else if (ConstantPoolSDNode *CP =
|
|
dyn_cast<ConstantPoolSDNode>(Address)) {
|
|
unsigned CPIdx = BB->getParent()->getConstantPool()->
|
|
getConstantPoolIndex(CP->get());
|
|
AlphaLowering.restoreGP(BB);
|
|
has_sym = true;
|
|
Tmp1 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPIdx)
|
|
.addReg(Alpha::R29);
|
|
if (EnableAlphaLSMark)
|
|
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
|
|
.addImm(getUID());
|
|
BuildMI(BB, GetRelVersion(Opc), 2, Result)
|
|
.addConstantPoolIndex(CPIdx).addReg(Tmp1);
|
|
} else if(Address.getOpcode() == ISD::FrameIndex) {
|
|
if (EnableAlphaLSMark)
|
|
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
|
|
.addImm(getUID());
|
|
BuildMI(BB, Opc, 2, Result)
|
|
.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
|
|
.addReg(Alpha::F31);
|
|
} else {
|
|
long offset;
|
|
SelectAddr(Address, Tmp1, offset);
|
|
if (EnableAlphaLSMark)
|
|
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
|
|
.addImm(getUID());
|
|
BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
|
|
}
|
|
return Result;
|
|
}
|
|
|
|
case ISD::GlobalAddress:
|
|
AlphaLowering.restoreGP(BB);
|
|
has_sym = true;
|
|
|
|
Reg = Result = MakeReg(MVT::i64);
|
|
|
|
if (EnableAlphaLSMark)
|
|
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
|
|
.addImm(getUID());
|
|
|
|
BuildMI(BB, Alpha::LDQl, 2, Result)
|
|
.addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal())
|
|
.addReg(Alpha::R29);
|
|
return Result;
|
|
|
|
case ISD::ExternalSymbol:
|
|
AlphaLowering.restoreGP(BB);
|
|
has_sym = true;
|
|
|
|
Reg = Result = MakeReg(MVT::i64);
|
|
|
|
if (EnableAlphaLSMark)
|
|
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
|
|
.addImm(getUID());
|
|
|
|
BuildMI(BB, Alpha::LDQl, 2, Result)
|
|
.addExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol())
|
|
.addReg(Alpha::R29);
|
|
return Result;
|
|
|
|
case ISD::TAILCALL:
|
|
case ISD::CALL:
|
|
{
|
|
Select(N.getOperand(0));
|
|
|
|
// The chain for this call is now lowered.
|
|
ExprMap[N.getValue(Node->getNumValues()-1)] = notIn;
|
|
|
|
//grab the arguments
|
|
std::vector<unsigned> argvregs;
|
|
//assert(Node->getNumOperands() < 8 && "Only 6 args supported");
|
|
for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
|
|
argvregs.push_back(SelectExpr(N.getOperand(i)));
|
|
|
|
//in reg args
|
|
for(int i = 0, e = std::min(6, (int)argvregs.size()); i < e; ++i)
|
|
{
|
|
unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
|
|
Alpha::R19, Alpha::R20, Alpha::R21};
|
|
unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
|
|
Alpha::F19, Alpha::F20, Alpha::F21};
|
|
switch(N.getOperand(i+2).getValueType()) {
|
|
default:
|
|
Node->dump();
|
|
N.getOperand(i).Val->dump();
|
|
std::cerr << "Type for " << i << " is: " <<
|
|
N.getOperand(i+2).getValueType() << "\n";
|
|
assert(0 && "Unknown value type for call");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
case MVT::i64:
|
|
BuildMI(BB, Alpha::BIS, 2, args_int[i]).addReg(argvregs[i])
|
|
.addReg(argvregs[i]);
|
|
break;
|
|
case MVT::f32:
|
|
case MVT::f64:
|
|
BuildMI(BB, Alpha::CPYS, 2, args_float[i]).addReg(argvregs[i])
|
|
.addReg(argvregs[i]);
|
|
break;
|
|
}
|
|
}
|
|
//in mem args
|
|
for (int i = 6, e = argvregs.size(); i < e; ++i)
|
|
{
|
|
switch(N.getOperand(i+2).getValueType()) {
|
|
default:
|
|
Node->dump();
|
|
N.getOperand(i).Val->dump();
|
|
std::cerr << "Type for " << i << " is: " <<
|
|
N.getOperand(i+2).getValueType() << "\n";
|
|
assert(0 && "Unknown value type for call");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
case MVT::i64:
|
|
BuildMI(BB, Alpha::STQ, 3).addReg(argvregs[i]).addImm((i - 6) * 8)
|
|
.addReg(Alpha::R30);
|
|
break;
|
|
case MVT::f32:
|
|
BuildMI(BB, Alpha::STS, 3).addReg(argvregs[i]).addImm((i - 6) * 8)
|
|
.addReg(Alpha::R30);
|
|
break;
|
|
case MVT::f64:
|
|
BuildMI(BB, Alpha::STT, 3).addReg(argvregs[i]).addImm((i - 6) * 8)
|
|
.addReg(Alpha::R30);
|
|
break;
|
|
}
|
|
}
|
|
//build the right kind of call
|
|
GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(N.getOperand(1));
|
|
if (GASD && !GASD->getGlobal()->isExternal()) {
|
|
//use PC relative branch call
|
|
AlphaLowering.restoreGP(BB);
|
|
BuildMI(BB, Alpha::BSR, 1, Alpha::R26)
|
|
.addGlobalAddress(GASD->getGlobal(),true);
|
|
} else {
|
|
//no need to restore GP as we are doing an indirect call
|
|
Tmp1 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp1).addReg(Tmp1);
|
|
BuildMI(BB, Alpha::JSR, 2, Alpha::R26).addReg(Alpha::R27).addImm(0);
|
|
}
|
|
|
|
//push the result into a virtual register
|
|
|
|
switch (Node->getValueType(0)) {
|
|
default: Node->dump(); assert(0 && "Unknown value type for call result!");
|
|
case MVT::Other: return notIn;
|
|
case MVT::i64:
|
|
BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0);
|
|
break;
|
|
case MVT::f32:
|
|
case MVT::f64:
|
|
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F0).addReg(Alpha::F0);
|
|
break;
|
|
}
|
|
return Result+N.ResNo;
|
|
}
|
|
|
|
case ISD::SIGN_EXTEND_INREG:
|
|
{
|
|
//do SDIV opt for all levels of ints if not dividing by a constant
|
|
if (EnableAlphaIDIV && N.getOperand(0).getOpcode() == ISD::SDIV
|
|
&& N.getOperand(0).getOperand(1).getOpcode() != ISD::Constant)
|
|
{
|
|
unsigned Tmp4 = MakeReg(MVT::f64);
|
|
unsigned Tmp5 = MakeReg(MVT::f64);
|
|
unsigned Tmp6 = MakeReg(MVT::f64);
|
|
unsigned Tmp7 = MakeReg(MVT::f64);
|
|
unsigned Tmp8 = MakeReg(MVT::f64);
|
|
unsigned Tmp9 = MakeReg(MVT::f64);
|
|
|
|
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
|
|
MoveInt2FP(Tmp1, Tmp4, true);
|
|
MoveInt2FP(Tmp2, Tmp5, true);
|
|
BuildMI(BB, Alpha::CVTQT, 1, Tmp6).addReg(Alpha::F31).addReg(Tmp4);
|
|
BuildMI(BB, Alpha::CVTQT, 1, Tmp7).addReg(Alpha::F31).addReg(Tmp5);
|
|
BuildMI(BB, Alpha::DIVT, 2, Tmp8).addReg(Tmp6).addReg(Tmp7);
|
|
BuildMI(BB, Alpha::CVTTQ, 1, Tmp9).addReg(Alpha::F31).addReg(Tmp8);
|
|
MoveFP2Int(Tmp9, Result, true);
|
|
return Result;
|
|
}
|
|
|
|
//Alpha has instructions for a bunch of signed 32 bit stuff
|
|
if(cast<VTSDNode>(Node->getOperand(1))->getVT() == MVT::i32) {
|
|
switch (N.getOperand(0).getOpcode()) {
|
|
case ISD::ADD:
|
|
case ISD::SUB:
|
|
case ISD::MUL:
|
|
{
|
|
bool isAdd = N.getOperand(0).getOpcode() == ISD::ADD;
|
|
bool isMul = N.getOperand(0).getOpcode() == ISD::MUL;
|
|
//FIXME: first check for Scaled Adds and Subs!
|
|
if(!isMul && N.getOperand(0).getOperand(0).getOpcode() == ISD::SHL &&
|
|
isSIntImmediateBounded(N.getOperand(0).getOperand(0).getOperand(1), SImm, 2, 3))
|
|
{
|
|
bool use4 = SImm == 2;
|
|
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
|
|
BuildMI(BB, isAdd?(use4?Alpha::S4ADDL:Alpha::S8ADDL):(use4?Alpha::S4SUBL:Alpha::S8SUBL),
|
|
2,Result).addReg(Tmp1).addReg(Tmp2);
|
|
}
|
|
else if(isAdd && N.getOperand(0).getOperand(1).getOpcode() == ISD::SHL &&
|
|
isSIntImmediateBounded(N.getOperand(0).getOperand(1).getOperand(1), SImm, 2, 3))
|
|
{
|
|
bool use4 = SImm == 2;
|
|
Tmp1 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
|
|
BuildMI(BB, use4?Alpha::S4ADDL:Alpha::S8ADDL, 2,Result).addReg(Tmp1).addReg(Tmp2);
|
|
}
|
|
else if(isSIntImmediateBounded(N.getOperand(0).getOperand(1), SImm, 0, 255))
|
|
{ //Normal imm add/sub
|
|
Opc = isAdd ? Alpha::ADDLi : (isMul ? Alpha::MULLi : Alpha::SUBLi);
|
|
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
|
|
}
|
|
else if(!isMul && isSIntImmediate(N.getOperand(0).getOperand(1), SImm) &&
|
|
(((SImm << 32) >> 32) >= -255) && (((SImm << 32) >> 32) <= 0))
|
|
{ //handle canonicalization
|
|
Opc = isAdd ? Alpha::SUBLi : Alpha::ADDLi;
|
|
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
|
|
SImm = 0 - ((SImm << 32) >> 32);
|
|
assert(SImm >= 0 && SImm <= 255);
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
|
|
}
|
|
else
|
|
{ //Normal add/sub
|
|
Opc = isAdd ? Alpha::ADDL : (isMul ? Alpha::MULL : Alpha::SUBL);
|
|
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
}
|
|
return Result;
|
|
}
|
|
default: break; //Fall Though;
|
|
}
|
|
} //Every thing else fall though too, including unhandled opcodes above
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
//std::cerr << "SrcT: " << MVN->getExtraValueType() << "\n";
|
|
switch(cast<VTSDNode>(Node->getOperand(1))->getVT()) {
|
|
default:
|
|
Node->dump();
|
|
assert(0 && "Sign Extend InReg not there yet");
|
|
break;
|
|
case MVT::i32:
|
|
{
|
|
BuildMI(BB, Alpha::ADDLi, 2, Result).addReg(Tmp1).addImm(0);
|
|
break;
|
|
}
|
|
case MVT::i16:
|
|
BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
|
|
break;
|
|
case MVT::i8:
|
|
BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Alpha::R31).addReg(Tmp1);
|
|
break;
|
|
case MVT::i1:
|
|
Tmp2 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::ANDi, 2, Tmp2).addReg(Tmp1).addImm(1);
|
|
BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(Alpha::R31).addReg(Tmp2);
|
|
break;
|
|
}
|
|
return Result;
|
|
}
|
|
|
|
case ISD::SETCC:
|
|
{
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(N.getOperand(2))->get();
|
|
if (MVT::isInteger(N.getOperand(0).getValueType())) {
|
|
bool isConst = false;
|
|
int dir;
|
|
|
|
//Tmp1 = SelectExpr(N.getOperand(0));
|
|
if(isSIntImmediate(N.getOperand(1), SImm) && SImm <= 255 && SImm >= 0)
|
|
isConst = true;
|
|
|
|
switch (CC) {
|
|
default: Node->dump(); assert(0 && "Unknown integer comparison!");
|
|
case ISD::SETEQ:
|
|
Opc = isConst ? Alpha::CMPEQi : Alpha::CMPEQ; dir=1; break;
|
|
case ISD::SETLT:
|
|
Opc = isConst ? Alpha::CMPLTi : Alpha::CMPLT; dir = 1; break;
|
|
case ISD::SETLE:
|
|
Opc = isConst ? Alpha::CMPLEi : Alpha::CMPLE; dir = 1; break;
|
|
case ISD::SETGT: Opc = Alpha::CMPLT; dir = 2; break;
|
|
case ISD::SETGE: Opc = Alpha::CMPLE; dir = 2; break;
|
|
case ISD::SETULT:
|
|
Opc = isConst ? Alpha::CMPULTi : Alpha::CMPULT; dir = 1; break;
|
|
case ISD::SETUGT: Opc = Alpha::CMPULT; dir = 2; break;
|
|
case ISD::SETULE:
|
|
Opc = isConst ? Alpha::CMPULEi : Alpha::CMPULE; dir = 1; break;
|
|
case ISD::SETUGE: Opc = Alpha::CMPULE; dir = 2; break;
|
|
case ISD::SETNE: {//Handle this one special
|
|
//std::cerr << "Alpha does not have a setne.\n";
|
|
//abort();
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
Tmp3 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::CMPEQ, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
|
|
//Remeber we have the Inv for this CC
|
|
CCInvMap[N] = Tmp3;
|
|
//and invert
|
|
BuildMI(BB, Alpha::CMPEQ, 2, Result).addReg(Alpha::R31).addReg(Tmp3);
|
|
return Result;
|
|
}
|
|
}
|
|
if (dir == 1) {
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
if (isConst) {
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
|
|
} else {
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
}
|
|
} else { //if (dir == 2) {
|
|
Tmp1 = SelectExpr(N.getOperand(1));
|
|
Tmp2 = SelectExpr(N.getOperand(0));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
}
|
|
} else {
|
|
//do the comparison
|
|
Tmp1 = MakeReg(MVT::f64);
|
|
bool inv = SelectFPSetCC(N, Tmp1);
|
|
|
|
//now arrange for Result (int) to have a 1 or 0
|
|
Tmp2 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::ADDQi, 2, Tmp2).addReg(Alpha::R31).addImm(1);
|
|
Opc = inv?Alpha::CMOVNEi_FP:Alpha::CMOVEQi_FP;
|
|
BuildMI(BB, Opc, 3, Result).addReg(Tmp2).addImm(0).addReg(Tmp1);
|
|
}
|
|
return Result;
|
|
}
|
|
|
|
case ISD::CopyFromReg:
|
|
{
|
|
++count_ins;
|
|
|
|
// Make sure we generate both values.
|
|
if (Result != notIn)
|
|
ExprMap[N.getValue(1)] = notIn; // Generate the token
|
|
else
|
|
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
|
|
|
|
SDOperand Chain = N.getOperand(0);
|
|
|
|
Select(Chain);
|
|
unsigned r = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
|
//std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
|
|
if (MVT::isFloatingPoint(N.getValue(0).getValueType()))
|
|
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
|
|
else
|
|
BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
|
|
return Result;
|
|
}
|
|
|
|
//Most of the plain arithmetic and logic share the same form, and the same
|
|
//constant immediate test
|
|
case ISD::XOR:
|
|
//Match Not
|
|
if (isSIntImmediate(N.getOperand(1), SImm) && SImm == -1) {
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
BuildMI(BB, Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp1);
|
|
return Result;
|
|
}
|
|
//Fall through
|
|
case ISD::AND:
|
|
//handle zap
|
|
if (opcode == ISD::AND && isUIntImmediate(N.getOperand(1), UImm))
|
|
{
|
|
unsigned int build = 0;
|
|
for(int i = 0; i < 8; ++i)
|
|
{
|
|
if ((UImm & 0x00FF) == 0x00FF)
|
|
build |= 1 << i;
|
|
else if ((UImm & 0x00FF) != 0)
|
|
{ build = 0; break; }
|
|
UImm >>= 8;
|
|
}
|
|
if (build)
|
|
{
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
BuildMI(BB, Alpha::ZAPNOTi, 2, Result).addReg(Tmp1).addImm(build);
|
|
return Result;
|
|
}
|
|
}
|
|
case ISD::OR:
|
|
//Check operand(0) == Not
|
|
if (N.getOperand(0).getOpcode() == ISD::XOR &&
|
|
isSIntImmediate(N.getOperand(0).getOperand(1), SImm) && SImm == -1) {
|
|
switch(opcode) {
|
|
case ISD::AND: Opc = Alpha::BIC; break;
|
|
case ISD::OR: Opc = Alpha::ORNOT; break;
|
|
case ISD::XOR: Opc = Alpha::EQV; break;
|
|
}
|
|
Tmp1 = SelectExpr(N.getOperand(1));
|
|
Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
return Result;
|
|
}
|
|
//Check operand(1) == Not
|
|
if (N.getOperand(1).getOpcode() == ISD::XOR &&
|
|
isSIntImmediate(N.getOperand(1).getOperand(1), SImm) && SImm == -1) {
|
|
switch(opcode) {
|
|
case ISD::AND: Opc = Alpha::BIC; break;
|
|
case ISD::OR: Opc = Alpha::ORNOT; break;
|
|
case ISD::XOR: Opc = Alpha::EQV; break;
|
|
}
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
return Result;
|
|
}
|
|
//Fall through
|
|
case ISD::SHL:
|
|
case ISD::SRL:
|
|
case ISD::SRA:
|
|
case ISD::MUL:
|
|
if(isSIntImmediateBounded(N.getOperand(1), SImm, 0, 255)) {
|
|
switch(opcode) {
|
|
case ISD::AND: Opc = Alpha::ANDi; break;
|
|
case ISD::OR: Opc = Alpha::BISi; break;
|
|
case ISD::XOR: Opc = Alpha::XORi; break;
|
|
case ISD::SHL: Opc = Alpha::SLi; break;
|
|
case ISD::SRL: Opc = Alpha::SRLi; break;
|
|
case ISD::SRA: Opc = Alpha::SRAi; break;
|
|
case ISD::MUL: Opc = Alpha::MULQi; break;
|
|
};
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
|
|
} else {
|
|
switch(opcode) {
|
|
case ISD::AND: Opc = Alpha::AND; break;
|
|
case ISD::OR: Opc = Alpha::BIS; break;
|
|
case ISD::XOR: Opc = Alpha::XOR; break;
|
|
case ISD::SHL: Opc = Alpha::SL; break;
|
|
case ISD::SRL: Opc = Alpha::SRL; break;
|
|
case ISD::SRA: Opc = Alpha::SRA; break;
|
|
case ISD::MUL: Opc = Alpha::MULQ; break;
|
|
};
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
}
|
|
return Result;
|
|
|
|
case ISD::ADD:
|
|
case ISD::SUB:
|
|
{
|
|
bool isAdd = opcode == ISD::ADD;
|
|
|
|
//first check for Scaled Adds and Subs!
|
|
//Valid for add and sub
|
|
if(N.getOperand(0).getOpcode() == ISD::SHL &&
|
|
isSIntImmediate(N.getOperand(0).getOperand(1), SImm) &&
|
|
(SImm == 2 || SImm == 3)) {
|
|
bool use4 = SImm == 2;
|
|
Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
|
|
if (isSIntImmediateBounded(N.getOperand(1), SImm, 0, 255))
|
|
BuildMI(BB, isAdd?(use4?Alpha::S4ADDQi:Alpha::S8ADDQi):(use4?Alpha::S4SUBQi:Alpha::S8SUBQi),
|
|
2, Result).addReg(Tmp2).addImm(SImm);
|
|
else {
|
|
Tmp1 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, isAdd?(use4?Alpha::S4ADDQi:Alpha::S8ADDQi):(use4?Alpha::S4SUBQi:Alpha::S8SUBQi),
|
|
2, Result).addReg(Tmp2).addReg(Tmp1);
|
|
}
|
|
}
|
|
//Position prevents subs
|
|
else if(N.getOperand(1).getOpcode() == ISD::SHL && isAdd &&
|
|
isSIntImmediate(N.getOperand(1).getOperand(1), SImm) &&
|
|
(SImm == 2 || SImm == 3)) {
|
|
bool use4 = SImm == 2;
|
|
Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
|
|
if (isSIntImmediateBounded(N.getOperand(0), SImm, 0, 255))
|
|
BuildMI(BB, use4?Alpha::S4ADDQi:Alpha::S8ADDQi, 2, Result).addReg(Tmp2).addImm(SImm);
|
|
else {
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
BuildMI(BB, use4?Alpha::S4ADDQ:Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
|
|
}
|
|
}
|
|
//small addi
|
|
else if(isSIntImmediateBounded(N.getOperand(1), SImm, 0, 255))
|
|
{ //Normal imm add/sub
|
|
Opc = isAdd ? Alpha::ADDQi : Alpha::SUBQi;
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(SImm);
|
|
}
|
|
else if(isSIntImmediateBounded(N.getOperand(1), SImm, -255, 0))
|
|
{ //inverted imm add/sub
|
|
Opc = isAdd ? Alpha::SUBQi : Alpha::ADDQi;
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(-SImm);
|
|
}
|
|
//larger addi
|
|
else if(isSIntImmediateBounded(N.getOperand(1), SImm, -32767, 32767))
|
|
{ //LDA
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
if (!isAdd)
|
|
SImm = -SImm;
|
|
BuildMI(BB, Alpha::LDA, 2, Result).addImm(SImm).addReg(Tmp1);
|
|
}
|
|
//give up and do the operation
|
|
else {
|
|
//Normal add/sub
|
|
Opc = isAdd ? Alpha::ADDQ : Alpha::SUBQ;
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
}
|
|
return Result;
|
|
}
|
|
case ISD::FADD:
|
|
case ISD::FSUB:
|
|
case ISD::FMUL:
|
|
case ISD::FDIV: {
|
|
if (opcode == ISD::FADD)
|
|
Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS;
|
|
else if (opcode == ISD::FSUB)
|
|
Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS;
|
|
else if (opcode == ISD::FMUL)
|
|
Opc = DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS;
|
|
else
|
|
Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS;
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
|
|
return Result;
|
|
}
|
|
case ISD::SDIV:
|
|
{
|
|
//check if we can convert into a shift!
|
|
if (isSIntImmediate(N.getOperand(1), SImm) &&
|
|
SImm != 0 && isPowerOf2_64(llabs(SImm))) {
|
|
unsigned k = Log2_64(llabs(SImm));
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
if (k == 1)
|
|
Tmp2 = Tmp1;
|
|
else
|
|
{
|
|
Tmp2 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::SRAi, 2, Tmp2).addReg(Tmp1).addImm(k - 1);
|
|
}
|
|
Tmp3 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::SRLi, 2, Tmp3).addReg(Tmp2).addImm(64-k);
|
|
unsigned Tmp4 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::ADDQ, 2, Tmp4).addReg(Tmp3).addReg(Tmp1);
|
|
if (SImm > 0)
|
|
BuildMI(BB, Alpha::SRAi, 2, Result).addReg(Tmp4).addImm(k);
|
|
else
|
|
{
|
|
unsigned Tmp5 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::SRAi, 2, Tmp5).addReg(Tmp4).addImm(k);
|
|
BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(Alpha::R31).addReg(Tmp5);
|
|
}
|
|
return Result;
|
|
}
|
|
}
|
|
//Else fall through
|
|
|
|
case ISD::UDIV:
|
|
{
|
|
if (isSIntImmediate(N.getOperand(1), SImm) && (SImm >= 2 || SImm <= -2))
|
|
{
|
|
// If this is a divide by constant, we can emit code using some magic
|
|
// constants to implement it as a multiply instead.
|
|
ExprMap.erase(N);
|
|
if (opcode == ISD::SDIV)
|
|
return SelectExpr(BuildSDIVSequence(N));
|
|
else
|
|
return SelectExpr(BuildUDIVSequence(N));
|
|
}
|
|
}
|
|
//else fall though
|
|
case ISD::UREM:
|
|
case ISD::SREM: {
|
|
const char* opstr = 0;
|
|
switch(opcode) {
|
|
case ISD::UREM: opstr = "__remqu"; break;
|
|
case ISD::SREM: opstr = "__remq"; break;
|
|
case ISD::UDIV: opstr = "__divqu"; break;
|
|
case ISD::SDIV: opstr = "__divq"; break;
|
|
}
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
Tmp2 = SelectExpr(N.getOperand(1));
|
|
SDOperand Addr =
|
|
ISelDAG->getExternalSymbol(opstr, AlphaLowering.getPointerTy());
|
|
Tmp3 = SelectExpr(Addr);
|
|
//set up regs explicitly (helps Reg alloc)
|
|
BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp1).addReg(Tmp1);
|
|
BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp2).addReg(Tmp2);
|
|
BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp3).addReg(Tmp3);
|
|
BuildMI(BB, Alpha::JSRs, 2, Alpha::R23).addReg(Alpha::R27).addImm(0);
|
|
BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R27).addReg(Alpha::R27);
|
|
return Result;
|
|
}
|
|
|
|
case ISD::FP_TO_UINT:
|
|
case ISD::FP_TO_SINT:
|
|
{
|
|
assert (DestType == MVT::i64 && "only quads can be loaded to");
|
|
MVT::ValueType SrcType = N.getOperand(0).getValueType();
|
|
assert (SrcType == MVT::f32 || SrcType == MVT::f64);
|
|
Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
|
|
if (SrcType == MVT::f32)
|
|
{
|
|
Tmp2 = MakeReg(MVT::f64);
|
|
BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1);
|
|
Tmp1 = Tmp2;
|
|
}
|
|
Tmp2 = MakeReg(MVT::f64);
|
|
BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1);
|
|
MoveFP2Int(Tmp2, Result, true);
|
|
|
|
return Result;
|
|
}
|
|
|
|
case ISD::SELECT:
|
|
if (isFP) {
|
|
//Tmp1 = SelectExpr(N.getOperand(0)); //Cond
|
|
unsigned TV = SelectExpr(N.getOperand(1)); //Use if TRUE
|
|
unsigned FV = SelectExpr(N.getOperand(2)); //Use if FALSE
|
|
|
|
SDOperand CC = N.getOperand(0);
|
|
|
|
if (CC.getOpcode() == ISD::SETCC &&
|
|
!MVT::isInteger(CC.getOperand(0).getValueType())) {
|
|
//FP Setcc -> Select yay!
|
|
|
|
|
|
//for a cmp b: c = a - b;
|
|
//a = b: c = 0
|
|
//a < b: c < 0
|
|
//a > b: c > 0
|
|
|
|
bool invTest = false;
|
|
unsigned Tmp3;
|
|
|
|
ConstantFPSDNode *CN;
|
|
if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(1)))
|
|
&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
|
|
Tmp3 = SelectExpr(CC.getOperand(0));
|
|
else if ((CN = dyn_cast<ConstantFPSDNode>(CC.getOperand(0)))
|
|
&& (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
|
|
{
|
|
Tmp3 = SelectExpr(CC.getOperand(1));
|
|
invTest = true;
|
|
}
|
|
else
|
|
{
|
|
unsigned Tmp1 = SelectExpr(CC.getOperand(0));
|
|
unsigned Tmp2 = SelectExpr(CC.getOperand(1));
|
|
bool isD = CC.getOperand(0).getValueType() == MVT::f64;
|
|
Tmp3 = MakeReg(isD ? MVT::f64 : MVT::f32);
|
|
BuildMI(BB, isD ? Alpha::SUBT : Alpha::SUBS, 2, Tmp3)
|
|
.addReg(Tmp1).addReg(Tmp2);
|
|
}
|
|
|
|
switch (cast<CondCodeSDNode>(CC.getOperand(2))->get()) {
|
|
default: CC.Val->dump(); assert(0 && "Unknown FP comparison!");
|
|
case ISD::SETEQ: Opc = invTest ? Alpha::FCMOVNE : Alpha::FCMOVEQ; break;
|
|
case ISD::SETLT: Opc = invTest ? Alpha::FCMOVGT : Alpha::FCMOVLT; break;
|
|
case ISD::SETLE: Opc = invTest ? Alpha::FCMOVGE : Alpha::FCMOVLE; break;
|
|
case ISD::SETGT: Opc = invTest ? Alpha::FCMOVLT : Alpha::FCMOVGT; break;
|
|
case ISD::SETGE: Opc = invTest ? Alpha::FCMOVLE : Alpha::FCMOVGE; break;
|
|
case ISD::SETNE: Opc = invTest ? Alpha::FCMOVEQ : Alpha::FCMOVNE; break;
|
|
}
|
|
BuildMI(BB, Opc, 3, Result).addReg(FV).addReg(TV).addReg(Tmp3);
|
|
return Result;
|
|
}
|
|
else
|
|
{
|
|
Tmp1 = SelectExpr(N.getOperand(0)); //Cond
|
|
BuildMI(BB, Alpha::FCMOVEQ_INT, 3, Result).addReg(TV).addReg(FV)
|
|
.addReg(Tmp1);
|
|
// // Spill the cond to memory and reload it from there.
|
|
// unsigned Tmp4 = MakeReg(MVT::f64);
|
|
// MoveIntFP(Tmp1, Tmp4, true);
|
|
// //now ideally, we don't have to do anything to the flag...
|
|
// // Get the condition into the zero flag.
|
|
// BuildMI(BB, Alpha::FCMOVEQ, 3, Result).addReg(TV).addReg(FV).addReg(Tmp4);
|
|
return Result;
|
|
}
|
|
} else {
|
|
//FIXME: look at parent to decide if intCC can be folded, or if setCC(FP)
|
|
//and can save stack use
|
|
//Tmp1 = SelectExpr(N.getOperand(0)); //Cond
|
|
//Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
|
|
//Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
|
|
// Get the condition into the zero flag.
|
|
//BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
|
|
|
|
SDOperand CC = N.getOperand(0);
|
|
|
|
if (CC.getOpcode() == ISD::SETCC &&
|
|
!MVT::isInteger(CC.getOperand(0).getValueType()))
|
|
{ //FP Setcc -> Int Select
|
|
Tmp1 = MakeReg(MVT::f64);
|
|
Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
|
|
Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
|
|
bool inv = SelectFPSetCC(CC, Tmp1);
|
|
BuildMI(BB, inv?Alpha::CMOVNE_FP:Alpha::CMOVEQ_FP, 2, Result)
|
|
.addReg(Tmp2).addReg(Tmp3).addReg(Tmp1);
|
|
return Result;
|
|
}
|
|
if (CC.getOpcode() == ISD::SETCC) {
|
|
//Int SetCC -> Select
|
|
//Dropping the CC is only useful if we are comparing to 0
|
|
if(isSIntImmediateBounded(CC.getOperand(1), SImm, 0, 0)) {
|
|
//figure out a few things
|
|
bool useImm = isSIntImmediateBounded(N.getOperand(2), SImm, 0, 255);
|
|
|
|
//Fix up CC
|
|
ISD::CondCode cCode= cast<CondCodeSDNode>(CC.getOperand(2))->get();
|
|
if (useImm) //Invert sense to get Imm field right
|
|
cCode = ISD::getSetCCInverse(cCode, true);
|
|
|
|
//Choose the CMOV
|
|
switch (cCode) {
|
|
default: CC.Val->dump(); assert(0 && "Unknown integer comparison!");
|
|
case ISD::SETEQ: Opc = useImm?Alpha::CMOVEQi:Alpha::CMOVEQ; break;
|
|
case ISD::SETLT: Opc = useImm?Alpha::CMOVLTi:Alpha::CMOVLT; break;
|
|
case ISD::SETLE: Opc = useImm?Alpha::CMOVLEi:Alpha::CMOVLE; break;
|
|
case ISD::SETGT: Opc = useImm?Alpha::CMOVGTi:Alpha::CMOVGT; break;
|
|
case ISD::SETGE: Opc = useImm?Alpha::CMOVGEi:Alpha::CMOVGE; break;
|
|
case ISD::SETULT: assert(0 && "unsigned < 0 is never true"); break;
|
|
case ISD::SETUGT: Opc = useImm?Alpha::CMOVNEi:Alpha::CMOVNE; break;
|
|
//Technically you could have this CC
|
|
case ISD::SETULE: Opc = useImm?Alpha::CMOVEQi:Alpha::CMOVEQ; break;
|
|
case ISD::SETUGE: assert(0 && "unsgined >= 0 is always true"); break;
|
|
case ISD::SETNE: Opc = useImm?Alpha::CMOVNEi:Alpha::CMOVNE; break;
|
|
}
|
|
Tmp1 = SelectExpr(CC.getOperand(0)); //Cond
|
|
|
|
if (useImm) {
|
|
Tmp3 = SelectExpr(N.getOperand(1)); //Use if FALSE
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp3).addImm(SImm).addReg(Tmp1);
|
|
} else {
|
|
Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
|
|
Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
|
|
BuildMI(BB, Opc, 2, Result).addReg(Tmp3).addReg(Tmp2).addReg(Tmp1);
|
|
}
|
|
return Result;
|
|
}
|
|
//Otherwise, fall though
|
|
}
|
|
Tmp1 = SelectExpr(N.getOperand(0)); //Cond
|
|
Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
|
|
Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
|
|
BuildMI(BB, Alpha::CMOVEQ, 2, Result).addReg(Tmp2).addReg(Tmp3)
|
|
.addReg(Tmp1);
|
|
|
|
return Result;
|
|
}
|
|
|
|
case ISD::Constant:
|
|
{
|
|
int64_t val = (int64_t)cast<ConstantSDNode>(N)->getValue();
|
|
int zero_extend_top = 0;
|
|
if (val > 0 && (val & 0xFFFFFFFF00000000ULL) == 0 &&
|
|
((int32_t)val < 0)) {
|
|
//try a small load and zero extend
|
|
val = (int32_t)val;
|
|
zero_extend_top = 15;
|
|
}
|
|
|
|
if (val <= IMM_HIGH && val >= IMM_LOW) {
|
|
if(!zero_extend_top)
|
|
BuildMI(BB, Alpha::LDA, 2, Result).addImm(val).addReg(Alpha::R31);
|
|
else {
|
|
Tmp1 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::LDA, 2, Tmp1).addImm(val).addReg(Alpha::R31);
|
|
BuildMI(BB, Alpha::ZAPNOT, 2, Result).addReg(Tmp1).addImm(zero_extend_top);
|
|
}
|
|
}
|
|
else if (val <= (int64_t)IMM_HIGH +(int64_t)IMM_HIGH* (int64_t)IMM_MULT &&
|
|
val >= (int64_t)IMM_LOW + (int64_t)IMM_LOW * (int64_t)IMM_MULT) {
|
|
Tmp1 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::LDAH, 2, Tmp1).addImm(getUpper16(val))
|
|
.addReg(Alpha::R31);
|
|
if (!zero_extend_top)
|
|
BuildMI(BB, Alpha::LDA, 2, Result).addImm(getLower16(val)).addReg(Tmp1);
|
|
else {
|
|
Tmp3 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::LDA, 2, Tmp3).addImm(getLower16(val)).addReg(Tmp1);
|
|
BuildMI(BB, Alpha::ZAPNOT, 2, Result).addReg(Tmp3).addImm(zero_extend_top);
|
|
}
|
|
}
|
|
else {
|
|
//re-get the val since we are going to mem anyway
|
|
val = (int64_t)cast<ConstantSDNode>(N)->getValue();
|
|
MachineConstantPool *CP = BB->getParent()->getConstantPool();
|
|
ConstantUInt *C =
|
|
ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , val);
|
|
unsigned CPI = CP->getConstantPoolIndex(C);
|
|
AlphaLowering.restoreGP(BB);
|
|
has_sym = true;
|
|
Tmp1 = MakeReg(MVT::i64);
|
|
BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CPI)
|
|
.addReg(Alpha::R29);
|
|
if (EnableAlphaLSMark)
|
|
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(5).addImm(0).addImm(0)
|
|
.addImm(getUID());
|
|
BuildMI(BB, Alpha::LDQr, 2, Result).addConstantPoolIndex(CPI)
|
|
.addReg(Tmp1);
|
|
}
|
|
return Result;
|
|
}
|
|
case ISD::FNEG:
|
|
if(ISD::FABS == N.getOperand(0).getOpcode())
|
|
{
|
|
Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
|
|
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
|
|
} else {
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp1).addReg(Tmp1);
|
|
}
|
|
return Result;
|
|
|
|
case ISD::FABS:
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31).addReg(Tmp1);
|
|
return Result;
|
|
|
|
case ISD::FP_ROUND:
|
|
assert (DestType == MVT::f32 &&
|
|
N.getOperand(0).getValueType() == MVT::f64 &&
|
|
"only f64 to f32 conversion supported here");
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Alpha::F31).addReg(Tmp1);
|
|
return Result;
|
|
|
|
case ISD::FP_EXTEND:
|
|
assert (DestType == MVT::f64 &&
|
|
N.getOperand(0).getValueType() == MVT::f32 &&
|
|
"only f32 to f64 conversion supported here");
|
|
Tmp1 = SelectExpr(N.getOperand(0));
|
|
BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Alpha::F31).addReg(Tmp1);
|
|
return Result;
|
|
|
|
case ISD::ConstantFP:
|
|
if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
|
|
if (CN->isExactlyValue(+0.0)) {
|
|
BuildMI(BB, Alpha::CPYS, 2, Result).addReg(Alpha::F31)
|
|
.addReg(Alpha::F31);
|
|
} else if ( CN->isExactlyValue(-0.0)) {
|
|
BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Alpha::F31)
|
|
.addReg(Alpha::F31);
|
|
} else {
|
|
abort();
|
|
}
|
|
}
|
|
return Result;
|
|
|
|
case ISD::SINT_TO_FP:
|
|
{
|
|
assert (N.getOperand(0).getValueType() == MVT::i64
|
|
&& "only quads can be loaded from");
|
|
Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
|
|
Tmp2 = MakeReg(MVT::f64);
|
|
MoveInt2FP(Tmp1, Tmp2, true);
|
|
Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
|
|
BuildMI(BB, Opc, 1, Result).addReg(Alpha::F31).addReg(Tmp2);
|
|
return Result;
|
|
}
|
|
|
|
case ISD::AssertSext:
|
|
case ISD::AssertZext:
|
|
return SelectExpr(N.getOperand(0));
|
|
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void AlphaISel::Select(SDOperand N) {
|
|
unsigned Tmp1, Tmp2, Opc;
|
|
unsigned opcode = N.getOpcode();
|
|
|
|
if (!ExprMap.insert(std::make_pair(N, notIn)).second)
|
|
return; // Already selected.
|
|
|
|
SDNode *Node = N.Val;
|
|
|
|
switch (opcode) {
|
|
|
|
default:
|
|
Node->dump(); std::cerr << "\n";
|
|
assert(0 && "Node not handled yet!");
|
|
|
|
case ISD::BRCOND: {
|
|
SelectBranchCC(N);
|
|
return;
|
|
}
|
|
|
|
case ISD::BR: {
|
|
MachineBasicBlock *Dest =
|
|
cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
|
|
|
|
Select(N.getOperand(0));
|
|
BuildMI(BB, Alpha::BR, 1, Alpha::R31).addMBB(Dest);
|
|
return;
|
|
}
|
|
|
|
case ISD::ImplicitDef:
|
|
++count_ins;
|
|
Select(N.getOperand(0));
|
|
BuildMI(BB, Alpha::IDEF, 0,
|
|
cast<RegisterSDNode>(N.getOperand(1))->getReg());
|
|
return;
|
|
|
|
case ISD::EntryToken: return; // Noop
|
|
|
|
case ISD::TokenFactor:
|
|
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
|
|
Select(Node->getOperand(i));
|
|
|
|
//N.Val->dump(); std::cerr << "\n";
|
|
//assert(0 && "Node not handled yet!");
|
|
|
|
return;
|
|
|
|
case ISD::CopyToReg:
|
|
++count_outs;
|
|
Select(N.getOperand(0));
|
|
Tmp1 = SelectExpr(N.getOperand(2));
|
|
Tmp2 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
|
|
|
|
if (Tmp1 != Tmp2) {
|
|
if (N.getOperand(2).getValueType() == MVT::f64 ||
|
|
N.getOperand(2).getValueType() == MVT::f32)
|
|
BuildMI(BB, Alpha::CPYS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
|
|
else
|
|
BuildMI(BB, Alpha::BIS, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
|
|
}
|
|
return;
|
|
|
|
case ISD::RET:
|
|
++count_outs;
|
|
switch (N.getNumOperands()) {
|
|
default:
|
|
std::cerr << N.getNumOperands() << "\n";
|
|
for (unsigned i = 0; i < N.getNumOperands(); ++i)
|
|
std::cerr << N.getOperand(i).getValueType() << "\n";
|
|
Node->dump();
|
|
assert(0 && "Unknown return instruction!");
|
|
case 2:
|
|
Select(N.getOperand(0));
|
|
Tmp1 = SelectExpr(N.getOperand(1));
|
|
switch (N.getOperand(1).getValueType()) {
|
|
default: Node->dump();
|
|
assert(0 && "All other types should have been promoted!!");
|
|
case MVT::f64:
|
|
case MVT::f32:
|
|
BuildMI(BB, Alpha::CPYS, 2, Alpha::F0).addReg(Tmp1).addReg(Tmp1);
|
|
break;
|
|
case MVT::i32:
|
|
case MVT::i64:
|
|
BuildMI(BB, Alpha::BIS, 2, Alpha::R0).addReg(Tmp1).addReg(Tmp1);
|
|
break;
|
|
}
|
|
break;
|
|
case 1:
|
|
Select(N.getOperand(0));
|
|
break;
|
|
}
|
|
// Just emit a 'ret' instruction
|
|
AlphaLowering.restoreRA(BB);
|
|
BuildMI(BB, Alpha::RET, 2, Alpha::R31).addReg(Alpha::R26).addImm(1);
|
|
return;
|
|
|
|
case ISD::TRUNCSTORE:
|
|
case ISD::STORE:
|
|
{
|
|
SDOperand Chain = N.getOperand(0);
|
|
SDOperand Value = N.getOperand(1);
|
|
SDOperand Address = N.getOperand(2);
|
|
Select(Chain);
|
|
|
|
Tmp1 = SelectExpr(Value); //value
|
|
|
|
if (opcode == ISD::STORE) {
|
|
switch(Value.getValueType()) {
|
|
default: assert(0 && "unknown Type in store");
|
|
case MVT::i64: Opc = Alpha::STQ; break;
|
|
case MVT::f64: Opc = Alpha::STT; break;
|
|
case MVT::f32: Opc = Alpha::STS; break;
|
|
}
|
|
} else { //ISD::TRUNCSTORE
|
|
switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) {
|
|
default: assert(0 && "unknown Type in store");
|
|
case MVT::i1: //FIXME: DAG does not promote this load
|
|
case MVT::i8: Opc = Alpha::STB; break;
|
|
case MVT::i16: Opc = Alpha::STW; break;
|
|
case MVT::i32: Opc = Alpha::STL; break;
|
|
}
|
|
}
|
|
|
|
int i, j, k;
|
|
if (EnableAlphaLSMark)
|
|
getValueInfo(cast<SrcValueSDNode>(N.getOperand(3))->getValue(),
|
|
i, j, k);
|
|
|
|
GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Address);
|
|
if (GASD && !GASD->getGlobal()->isExternal()) {
|
|
Tmp2 = MakeReg(MVT::i64);
|
|
AlphaLowering.restoreGP(BB);
|
|
BuildMI(BB, Alpha::LDAHr, 2, Tmp2)
|
|
.addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
|
|
if (EnableAlphaLSMark)
|
|
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
|
|
.addImm(getUID());
|
|
BuildMI(BB, GetRelVersion(Opc), 3).addReg(Tmp1)
|
|
.addGlobalAddress(GASD->getGlobal()).addReg(Tmp2);
|
|
} else if(Address.getOpcode() == ISD::FrameIndex) {
|
|
if (EnableAlphaLSMark)
|
|
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
|
|
.addImm(getUID());
|
|
BuildMI(BB, Opc, 3).addReg(Tmp1)
|
|
.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
|
|
.addReg(Alpha::F31);
|
|
} else {
|
|
long offset;
|
|
SelectAddr(Address, Tmp2, offset);
|
|
if (EnableAlphaLSMark)
|
|
BuildMI(BB, Alpha::MEMLABEL, 4).addImm(i).addImm(j).addImm(k)
|
|
.addImm(getUID());
|
|
BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
|
|
}
|
|
return;
|
|
}
|
|
|
|
case ISD::EXTLOAD:
|
|
case ISD::SEXTLOAD:
|
|
case ISD::ZEXTLOAD:
|
|
case ISD::LOAD:
|
|
case ISD::CopyFromReg:
|
|
case ISD::TAILCALL:
|
|
case ISD::CALL:
|
|
case ISD::DYNAMIC_STACKALLOC:
|
|
ExprMap.erase(N);
|
|
SelectExpr(N);
|
|
return;
|
|
|
|
case ISD::CALLSEQ_START:
|
|
case ISD::CALLSEQ_END:
|
|
Select(N.getOperand(0));
|
|
Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
|
|
|
|
Opc = N.getOpcode() == ISD::CALLSEQ_START ? Alpha::ADJUSTSTACKDOWN :
|
|
Alpha::ADJUSTSTACKUP;
|
|
BuildMI(BB, Opc, 1).addImm(Tmp1);
|
|
return;
|
|
|
|
case ISD::PCMARKER:
|
|
Select(N.getOperand(0)); //Chain
|
|
BuildMI(BB, Alpha::PCLABEL, 2)
|
|
.addImm( cast<ConstantSDNode>(N.getOperand(1))->getValue());
|
|
return;
|
|
}
|
|
assert(0 && "Should not be reached!");
|
|
}
|
|
|
|
|
|
/// createAlphaPatternInstructionSelector - This pass converts an LLVM function
|
|
/// into a machine code representation using pattern matching and a machine
|
|
/// description file.
|
|
///
|
|
FunctionPass *llvm::createAlphaPatternInstructionSelector(TargetMachine &TM) {
|
|
return new AlphaISel(TM);
|
|
}
|
|
|