mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8124020192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15586 91177308-0d34-0410-b5e6-96231b3b80d8
549 lines
14 KiB
TableGen
549 lines
14 KiB
TableGen
//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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class Format<bits<5> val> {
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bits<5> Value = val;
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}
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def Pseudo: Format<0>;
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def Gpr : Format<1>;
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def Gpr0 : Format<2>;
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def Simm16 : Format<3>;
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def Zimm16 : Format<4>;
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def PCRelimm24 : Format<5>;
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def Imm24 : Format<6>;
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def Imm5 : Format<7>;
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def PCRelimm14 : Format<8>;
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def Imm14 : Format<9>;
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def Imm2 : Format<10>;
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def Crf : Format<11>;
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def Imm3 : Format<12>;
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def Imm1 : Format<13>;
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def Fpr : Format<14>;
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def Imm4 : Format<15>;
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def Imm8 : Format<16>;
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def Disimm16 : Format<17>;
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def Disimm14 : Format<18>;
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def Spr : Format<19>;
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def Sgr : Format<20>;
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def Imm15 : Format<21>;
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def Vpr : Format<22>;
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//===----------------------------------------------------------------------===//
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//
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// PowerPC instruction formats
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class PPC32I<string name, bits<6> opcode, bit ppc64, bit vmx> : Instruction {
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field bits<32> Inst;
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bits<3> ArgCount;
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bits<5> Arg0Type;
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bits<5> Arg1Type;
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bits<5> Arg2Type;
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bits<5> Arg3Type;
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bits<5> Arg4Type;
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bit PPC64 = ppc64;
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bit VMX = vmx;
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let Name = name;
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let Namespace = "PPC32";
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let Inst{0-5} = opcode;
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}
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// 1.7.1 I-Form
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class IForm<string name, bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx>
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: PPC32I<name, opcode, ppc64, vmx> {
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field bits<24> LI;
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let ArgCount = 1;
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let Arg0Type = Imm24.Value;
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let Arg1Type = 0;
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let Arg2Type = 0;
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let Arg3Type = 0;
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let Arg4Type = 0;
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let Inst{6-29} = LI;
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let Inst{30} = aa;
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let Inst{31} = lk;
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}
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// 1.7.2 B-Form
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class BForm<string name, bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx>
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: PPC32I<name, opcode, ppc64, vmx> {
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field bits<5> BO;
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field bits<5> BI;
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field bits<14> BD;
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let ArgCount = 3;
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let Arg0Type = Imm5.Value;
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let Arg1Type = Imm5.Value;
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let Arg2Type = PCRelimm14.Value;
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let Arg3Type = 0;
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let Arg4Type = 0;
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let Inst{6-10} = BO;
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let Inst{11-15} = BI;
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let Inst{16-29} = BD;
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let Inst{30} = aa;
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let Inst{31} = lk;
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}
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class BForm_ext<string name, bits<6> opcode, bit aa, bit lk, bits<5> bo,
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bits<5> bi, bit ppc64, bit vmx>
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: BForm<name, opcode, aa, lk, ppc64, vmx> {
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let ArgCount = 2;
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let Arg2Type = Imm5.Value;
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let Arg1Type = PCRelimm14.Value;
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let Arg2Type = 0;
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let BO = bo;
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let BI = bi;
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}
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// 1.7.4 D-Form
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class DForm_base<string name, bits<6> opcode, bit ppc64, bit vmx>
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: PPC32I<name, opcode, ppc64, vmx> {
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field bits<5> A;
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field bits<5> B;
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field bits<16> C;
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let ArgCount = 3;
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let Arg0Type = Gpr.Value;
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let Arg1Type = Gpr.Value;
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let Arg2Type = Simm16.Value;
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let Arg3Type = 0;
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let Arg4Type = 0;
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let Inst{6-10} = A;
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let Inst{11-15} = B;
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let Inst{16-31} = C;
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}
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class DForm_1<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_base<name, opcode, ppc64, vmx> {
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let Arg1Type = Disimm16.Value;
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let Arg2Type = Gpr0.Value;
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}
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class DForm_2<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_base<name, opcode, ppc64, vmx>;
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class DForm_2_r0<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_base<name, opcode, ppc64, vmx> {
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let Arg1Type = Gpr0.Value;
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let B = 0;
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}
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// Currently we make the use/def reg distinction in ISel, not tablegen
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class DForm_3<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_1<name, opcode, ppc64, vmx>;
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class DForm_4<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_1<name, opcode, ppc64, vmx>;
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class DForm_4_zero<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_1<name, opcode, ppc64, vmx> {
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let ArgCount = 0;
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let Arg0Type = 0;
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let Arg1Type = 0;
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let Arg2Type = 0;
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let A = 0;
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let B = 0;
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let C = 0;
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}
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class DForm_5<string name, bits<6> opcode, bit ppc64, bit vmx>
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: PPC32I<name, opcode, ppc64, vmx> {
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field bits<3> BF;
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field bits<1> L;
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field bits<5> RA;
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field bits<16> I;
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let ArgCount = 4;
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let Arg0Type = Imm3.Value;
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let Arg1Type = Imm1.Value;
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let Arg2Type = Gpr.Value;
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let Arg3Type = Simm16.Value;
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let Arg4Type = 0;
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let Inst{6-8} = BF;
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let Inst{9} = 0;
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let Inst{10} = L;
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let Inst{11-15} = RA;
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let Inst{16-31} = I;
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}
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class DForm_5_ext<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_5<name, opcode, ppc64, vmx> {
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let L = 0;
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}
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class DForm_6<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_5<name, opcode, ppc64, vmx> {
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let Arg3Type = Zimm16.Value;
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}
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class DForm_6_ext<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_6<name, opcode, ppc64, vmx> {
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let L = 0;
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}
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class DForm_7<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_base<name, opcode, ppc64, vmx> {
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let Arg1Type = Imm5.Value;
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}
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class DForm_8<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_1<name, opcode, ppc64, vmx> {
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let Arg0Type = Fpr.Value;
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}
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class DForm_9<string name, bits<6> opcode, bit ppc64, bit vmx>
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: DForm_1<name, opcode, ppc64, vmx> {
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let Arg0Type = Fpr.Value;
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}
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// 1.7.6 X-Form
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class XForm_base_r3xo<string name, bits<6> opcode, bits<10> xo, bit rc,
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bit ppc64, bit vmx> : PPC32I<name, opcode, ppc64, vmx> {
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let ArgCount = 3;
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field bits<5> ST;
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field bits<5> A;
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field bits<5> B;
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let ArgCount = 3;
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let Arg0Type = Gpr.Value;
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let Arg1Type = Gpr.Value;
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let Arg2Type = Gpr.Value;
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let Arg3Type = 0;
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let Arg4Type = 0;
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let Inst{6-10} = ST;
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let Inst{11-15} = A;
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let Inst{16-20} = B;
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let Inst{21-30} = xo;
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let Inst{31} = rc;
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}
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class XForm_1<string name, bits<6> opcode, bits<10> xo, bit ppc64,
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bit vmx> : XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx>;
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class XForm_5<string name, bits<6> opcode, bits<10> xo, bit ppc64,
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bit vmx> : XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx> {
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let ArgCount = 1;
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let Arg1Type = 0;
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let Arg2Type = 0;
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let A = 0;
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let B = 0;
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}
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class XForm_6<string name, bits<6> opcode, bits<10> xo, bit rc, bit ppc64,
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bit vmx> : XForm_base_r3xo<name, opcode, xo, rc, ppc64, vmx>;
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class XForm_7<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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: XForm_base_r3xo<name, opcode, xo, 1, ppc64, vmx>;
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class XForm_8<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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: XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx>;
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class XForm_10<string name, bits<6> opcode, bits<10> xo, bit rc, bit ppc64,
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bit vmx> : XForm_base_r3xo<name, opcode, xo, rc, ppc64, vmx> {
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let Arg2Type = Imm5.Value;
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}
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class XForm_11<string name, bits<6> opcode, bits<10> xo, bit rc, bit ppc64,
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bit vmx> : XForm_base_r3xo<name, opcode, xo, rc, ppc64, vmx> {
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let ArgCount = 2;
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let Arg2Type = 0;
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let B = 0;
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}
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class XForm_16<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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: PPC32I<name, opcode, ppc64, vmx> {
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field bits<3> BF;
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field bits<1> L;
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field bits<5> RA;
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field bits<5> RB;
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let ArgCount = 4;
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let Arg0Type = Imm3.Value;
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let Arg1Type = Imm1.Value;
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let Arg2Type = Gpr.Value;
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let Arg3Type = Gpr.Value;
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let Arg4Type = 0;
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let Inst{6-8} = BF;
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let Inst{9} = 0;
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let Inst{10} = L;
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let Inst{11-15} = RA;
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let Inst{16-20} = RB;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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class XForm_16_ext<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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: XForm_16<name, opcode, xo, ppc64, vmx> {
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let L = 0;
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}
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class XForm_17<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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: PPC32I<name, opcode, ppc64, vmx> {
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field bits<3> BF;
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field bits<5> FRA;
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field bits<5> FRB;
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let ArgCount = 3;
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let Arg0Type = Imm3.Value;
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let Arg1Type = Fpr.Value;
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let Arg2Type = Fpr.Value;
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let Arg3Type = 0;
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let Arg4Type = 0;
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let Inst{6-8} = BF;
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let Inst{9-10} = 0;
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let Inst{11-15} = FRA;
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let Inst{16-20} = FRB;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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class XForm_25<string name, bits<6> opcode, bits<10> xo, bit ppc64,
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bit vmx> : XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx> {
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let Arg0Type = Fpr.Value;
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let Arg1Type = Gpr0.Value;
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}
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class XForm_26<string name, bits<6> opcode, bits<10> xo, bit rc, bit ppc64,
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bit vmx> : XForm_base_r3xo<name, opcode, xo, rc, ppc64, vmx> {
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let ArgCount = 2;
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let Arg0Type = Fpr.Value;
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let Arg1Type = Fpr.Value;
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let Arg2Type = 0;
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let A = 0;
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}
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class XForm_28<string name, bits<6> opcode, bits<10> xo, bit ppc64,
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bit vmx> : XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx> {
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let Arg0Type = Fpr.Value;
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let Arg1Type = Gpr0.Value;
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}
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// 1.7.7 XL-Form
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class XLForm_1<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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: XForm_base_r3xo<name, opcode, xo, 0, ppc64, vmx> {
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let Arg0Type = Imm5.Value;
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let Arg1Type = Imm5.Value;
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let Arg2Type = Imm5.Value;
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}
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class XLForm_2<string name, bits<6> opcode, bits<10> xo, bit lk, bit ppc64,
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bit vmx> : PPC32I<name, opcode, ppc64, vmx> {
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field bits<5> BO;
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field bits<5> BI;
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field bits<2> BH;
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let ArgCount = 3;
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let Arg0Type = Imm5.Value;
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let Arg1Type = Imm5.Value;
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let Arg2Type = Imm2.Value;
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let Arg3Type = 0;
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let Arg4Type = 0;
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let Inst{6-10} = BO;
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let Inst{11-15} = BI;
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let Inst{16-18} = 0;
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let Inst{19-20} = BH;
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let Inst{21-30} = xo;
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let Inst{31} = lk;
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}
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class XLForm_2_ext<string name, bits<6> opcode, bits<10> xo, bits<5> bo,
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bits<5> bi, bit lk, bit ppc64, bit vmx>
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: XLForm_2<name, opcode, xo, lk, ppc64, vmx> {
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let ArgCount = 0;
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let Arg0Type = 0;
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let Arg1Type = 0;
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let Arg2Type = 0;
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let BO = bo;
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let BI = bi;
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let BH = 0;
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}
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// 1.7.8 XFX-Form
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class XFXForm_1<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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: PPC32I<name, opcode, ppc64, vmx> {
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field bits<5> ST;
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field bits<10> SPR;
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let ArgCount = 2;
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let Arg0Type = Imm5.Value;
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let Arg1Type = Gpr.Value;
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let Arg2Type = 0;
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let Arg3Type = 0;
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let Arg4Type = 0;
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let Inst{6-10} = ST;
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let Inst{11-20} = SPR;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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class XFXForm_1_ext<string name, bits<6> opcode, bits<10> xo, bits<10> spr,
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bit ppc64, bit vmx> : XFXForm_1<name,opcode,xo,ppc64,vmx> {
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let ArgCount = 1;
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let Arg0Type = Gpr.Value;
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let Arg1Type = 0;
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let SPR = spr;
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}
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class XFXForm_7<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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: XFXForm_1<name, opcode, xo, ppc64, vmx>;
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class XFXForm_7_ext<string name, bits<6> opcode, bits<10> xo, bits<10> spr,
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bit ppc64, bit vmx> : XFXForm_7<name,opcode,xo,ppc64,vmx> {
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let ArgCount = 1;
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let Arg0Type = Gpr.Value;
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let Arg1Type = 0;
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let SPR = spr;
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}
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// 1.7.11 XO-Form
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class XOForm_1<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
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bit ppc64, bit vmx> : PPC32I<name, opcode, ppc64, vmx> {
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field bits<5> RT;
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field bits<5> RA;
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field bits<5> RB;
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let ArgCount = 3;
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let Arg0Type = Gpr.Value;
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let Arg1Type = Gpr.Value;
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let Arg2Type = Gpr.Value;
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let Arg3Type = 0;
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let Arg4Type = 0;
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let Inst{6-10} = RT;
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let Inst{11-15} = RA;
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let Inst{16-20} = RB;
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let Inst{21} = oe;
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let Inst{22-30} = xo;
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let Inst{31} = rc;
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}
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// This is a reversal of the two operands, used notably by extended ops SUB*:
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// sub x, y, z == subf x, z, y
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// subc x, y, z == subfc x, z, y
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class XOForm_1_rev<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
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bit ppc64, bit vmx>
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: XOForm_1<name, opcode, xo, oe, rc, ppc64, vmx> {
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let Inst{11-15} = RB;
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let Inst{16-20} = RA;
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}
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class XOForm_2<string name, bits<6> opcode, bits<9> xo, bit rc, bit ppc64,
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bit vmx> : XOForm_1<name, opcode, xo, 0, rc, ppc64, vmx>;
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class XOForm_3<string name, bits<6> opcode, bits<9> xo, bit oe, bit rc,
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bit ppc64, bit vmx> : XOForm_1<name,opcode,xo,oe,rc,ppc64,vmx> {
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let RB = 0;
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}
|
|
|
|
// 1.7.12 A-Form
|
|
class AForm_1<string name, bits<6> opcode, bits<5> xo, bit rc, bit ppc64,
|
|
bit vmx> : PPC32I<name, opcode, ppc64, vmx> {
|
|
let ArgCount = 4;
|
|
field bits<5> FRT;
|
|
field bits<5> FRA;
|
|
field bits<5> FRB;
|
|
field bits<5> FRC;
|
|
|
|
let Arg0Type = Fpr.Value;
|
|
let Arg1Type = Fpr.Value;
|
|
let Arg2Type = Fpr.Value;
|
|
let Arg3Type = Fpr.Value;
|
|
let Arg4Type = 0;
|
|
|
|
let Inst{6-10} = FRT;
|
|
let Inst{11-15} = FRA;
|
|
let Inst{16-20} = FRB;
|
|
let Inst{21-25} = FRC;
|
|
let Inst{26-30} = xo;
|
|
let Inst{31} = rc;
|
|
}
|
|
|
|
class AForm_2<string name, bits<6> opcode, bits<5> xo, bit rc, bit ppc64,
|
|
bit vmx> : AForm_1<name, opcode, xo, rc, ppc64, vmx> {
|
|
let ArgCount = 3;
|
|
let Arg3Type = 0;
|
|
let FRC = 0;
|
|
}
|
|
|
|
class AForm_3<string name, bits<6> opcode, bits<5> xo, bit rc, bit ppc64,
|
|
bit vmx> : AForm_1<name, opcode, xo, rc, ppc64, vmx> {
|
|
let ArgCount = 3;
|
|
let Arg3Type = 0;
|
|
let FRB = 0;
|
|
}
|
|
|
|
class AForm_4<string name, bits<6> opcode, bits<5> xo, bit rc, bit ppc64,
|
|
bit vmx> : AForm_1<name, opcode, xo, rc, ppc64, vmx> {
|
|
let ArgCount = 2;
|
|
let Arg2Type = 0;
|
|
let Arg3Type = 0;
|
|
let FRA = 0;
|
|
let FRC = 0;
|
|
}
|
|
|
|
// 1.7.13 M-Form
|
|
class MForm_1<string name, bits<6> opcode, bit rc, bit ppc64, bit vmx>
|
|
: PPC32I<name, opcode, ppc64, vmx> {
|
|
let ArgCount = 5;
|
|
field bits<5> RS;
|
|
field bits<5> RA;
|
|
field bits<5> RB;
|
|
field bits<5> MB;
|
|
field bits<5> ME;
|
|
|
|
let Arg0Type = Gpr.Value;
|
|
let Arg1Type = Gpr.Value;
|
|
let Arg2Type = Gpr.Value;
|
|
let Arg3Type = Imm5.Value;
|
|
let Arg4Type = Imm5.Value;
|
|
|
|
let Inst{6-10} = RS;
|
|
let Inst{11-15} = RA;
|
|
let Inst{16-20} = RB;
|
|
let Inst{21-25} = MB;
|
|
let Inst{26-30} = ME;
|
|
let Inst{31} = rc;
|
|
}
|
|
|
|
class MForm_2<string name, bits<6> opcode, bit rc, bit ppc64, bit vmx>
|
|
: MForm_1<name, opcode, rc, ppc64, vmx> {
|
|
let Arg2Type = Imm5.Value;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class Pseudo<string name> : PPC32I<name, 0, 0, 0> {
|
|
let Name = name;
|
|
let ArgCount = 0;
|
|
let PPC64 = 0;
|
|
let VMX = 0;
|
|
|
|
let Arg0Type = Pseudo.Value;
|
|
let Arg1Type = Pseudo.Value;
|
|
let Arg2Type = Pseudo.Value;
|
|
let Arg3Type = Pseudo.Value;
|
|
let Arg4Type = 0;
|
|
|
|
let Inst {31-0} = 0;
|
|
}
|