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https://github.com/c64scene-ar/llvm-6502.git
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524a60587d
push onto the top of the stack like x86, which uses the local area offset. This will allow the removal of PowerPCPEI.cpp soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15573 91177308-0d34-0410-b5e6-96231b3b80d8
279 lines
9.9 KiB
C++
279 lines
9.9 KiB
C++
//===- PowerPCRegisterInfo.cpp - PowerPC Register Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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#include "PowerPC.h"
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#include "PowerPCRegisterInfo.h"
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#include "PowerPCInstrBuilder.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "Support/CommandLine.h"
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#include "Support/Debug.h"
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#include "Support/STLExtras.h"
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#include <iostream>
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using namespace llvm;
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PowerPCRegisterInfo::PowerPCRegisterInfo()
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: PowerPCGenRegisterInfo(PPC32::ADJCALLSTACKDOWN,
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PPC32::ADJCALLSTACKUP) {}
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static unsigned getIdx(const TargetRegisterClass *RC) {
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if (RC == PowerPC::GPRCRegisterClass) {
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switch (RC->getSize()) {
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default: assert(0 && "Invalid data size!");
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case 1: return 0;
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case 2: return 1;
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case 4: return 2;
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}
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} else if (RC == PowerPC::FPRCRegisterClass) {
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switch (RC->getSize()) {
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default: assert(0 && "Invalid data size!");
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case 4: return 3;
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case 8: return 4;
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}
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}
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std::cerr << "Invalid register class to getIdx()!\n";
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abort();
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}
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int
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PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] = {
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PPC32::STB, PPC32::STH, PPC32::STW, PPC32::STFS, PPC32::STFD
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};
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unsigned OC = Opcode[getIdx(RC)];
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if (SrcReg == PPC32::LR) {
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MBB.insert(MI, BuildMI(PPC32::MFLR, 0, PPC32::R0));
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MBB.insert(MI, addFrameReference(BuildMI(OC,3).addReg(PPC32::R0),FrameIdx));
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return 2;
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} else {
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MBB.insert(MI, addFrameReference(BuildMI(OC, 3).addReg(SrcReg),FrameIdx));
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return 1;
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}
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}
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int
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PowerPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] = {
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PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS, PPC32::LFD
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};
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unsigned OC = Opcode[getIdx(RC)];
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if (DestReg == PPC32::LR) {
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MBB.insert(MI, addFrameReference(BuildMI(OC, 2, PPC32::R0), FrameIdx));
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MBB.insert(MI, BuildMI(PPC32::MTLR, 1).addReg(PPC32::R0));
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return 2;
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} else {
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MBB.insert(MI, addFrameReference(BuildMI(OC, 2, DestReg), FrameIdx));
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return 1;
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}
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}
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int PowerPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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MachineInstr *I;
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if (RC == PowerPC::GPRCRegisterClass) {
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I = BuildMI(PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (RC == PowerPC::FPRCRegisterClass) {
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I = BuildMI(PPC32::FMR, 1, DestReg).addReg(SrcReg);
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} else {
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std::cerr << "Attempt to copy register that is not GPR or FPR";
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abort();
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}
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MBB.insert(MI, I);
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return 1;
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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static bool hasFP(MachineFunction &MF) {
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return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
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}
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void PowerPCRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (hasFP(MF)) {
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// If we have a frame pointer, convert as follows:
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// ADJCALLSTACKDOWN -> addi, r1, r1, -amount
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// ADJCALLSTACKUP -> addi, r1, r1, amount
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MachineInstr *Old = I;
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unsigned Amount = Old->getOperand(0).getImmedValue();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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MachineInstr *New;
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if (Old->getOpcode() == PPC32::ADJCALLSTACKDOWN) {
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New = BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1)
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.addSImm(-Amount);
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} else {
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assert(Old->getOpcode() == PPC32::ADJCALLSTACKUP);
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New = BuildMI(PPC32::ADDI, 2, PPC32::R1).addReg(PPC32::R1)
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.addSImm(Amount);
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}
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// Replace the pseudo instruction with a new instruction...
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MBB.insert(I, New);
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}
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}
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MBB.erase(I);
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}
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void
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PowerPCRegisterInfo::eliminateFrameIndex(MachineFunction &MF,
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MachineBasicBlock::iterator II) const {
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unsigned i = 0;
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MachineInstr &MI = *II;
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// Replace the FrameIndex with base register with GPR1.
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MI.SetMachineOperandReg(i, PPC32::R1);
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// Take into account whether it's an add or mem instruction
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unsigned OffIdx = (i == 2) ? 1 : 2;
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// Now add the frame object offset to the offset from r1.
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(OffIdx).getImmedValue();
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// Fixed offsets have a negative frame index. Fixed negative offests denote
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// spilled callee save regs. Fixed positive offset is the va_start offset,
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// and needs to be added to the amount we decremented the stack pointer.
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// Positive frame indices are regular offsets from the stack pointer, and
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// also need the stack size added.
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if (FrameIndex >= 0 || (FrameIndex < 0 && Offset >= 24))
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Offset += MF.getFrameInfo()->getStackSize();
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MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
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}
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void PowerPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineInstr *MI;
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// Get the number of bytes to allocate from the FrameInfo
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unsigned NumBytes = MFI->getStackSize();
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// If we have calls, we cannot use the red zone to store callee save registers
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// and we must set up a stack frame, so calculate the necessary size here.
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if (MFI->hasCalls()) {
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// We reserve argument space for call sites in the function immediately on
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// entry to the current function. This eliminates the need for add/sub
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// brackets around call sites.
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NumBytes += MFI->getMaxCallFrameSize();
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}
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// Do we need to allocate space on the stack?
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if (NumBytes == 0) return;
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// Add the size of R1 to NumBytes size for the store of R1 to the bottom
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// of the stack and round the size to a multiple of the alignment.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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unsigned Size = getRegClass(PPC32::R1)->getSize();
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NumBytes = (NumBytes+Size+Align-1)/Align*Align;
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// Update frame info to pretend that this is part of the stack...
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MFI->setStackSize(NumBytes);
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// adjust stack pointer: r1 -= numbytes
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if (NumBytes <= 32768) {
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MI = BuildMI(PPC32::STWU, 3).addReg(PPC32::R1).addSImm(-NumBytes)
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.addReg(PPC32::R1);
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MBB.insert(MBBI, MI);
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} else {
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int NegNumbytes = -NumBytes;
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MI = BuildMI(PPC32::LIS, 1, PPC32::R0).addSImm(NegNumbytes >> 16);
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MBB.insert(MBBI, MI);
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MI = BuildMI(PPC32::ORI, 2, PPC32::R0).addReg(PPC32::R0)
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.addImm(NegNumbytes & 0xFFFF);
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MBB.insert(MBBI, MI);
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MI = BuildMI(PPC32::STWUX, 3).addReg(PPC32::R1).addReg(PPC32::R1)
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.addReg(PPC32::R0);
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MBB.insert(MBBI, MI);
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}
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}
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void PowerPCRegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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MachineInstr *MI;
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assert(MBBI->getOpcode() == PPC32::BLR &&
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"Can only insert epilog into returning blocks");
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// Get the number of bytes allocated from the FrameInfo...
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unsigned NumBytes = MFI->getStackSize();
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if (NumBytes != 0) {
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MI = BuildMI(PPC32::LWZ, 2, PPC32::R1).addSImm(0).addReg(PPC32::R1);
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MBB.insert(MBBI, MI);
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}
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}
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#include "PowerPCGenRegisterInfo.inc"
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const TargetRegisterClass*
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PowerPCRegisterInfo::getRegClassForType(const Type* Ty) const {
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switch (Ty->getTypeID()) {
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case Type::LongTyID:
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case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
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default: assert(0 && "Invalid type to getClass!");
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case Type::BoolTyID:
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case Type::SByteTyID:
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case Type::UByteTyID:
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case Type::ShortTyID:
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case Type::UShortTyID:
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return &GPRCInstance;
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case Type::FloatTyID:
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case Type::DoubleTyID: return &FPRCInstance;
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}
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}
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