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https://github.com/c64scene-ar/llvm-6502.git
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b503b49b51
This adds all CodeGen tests for the SystemZ target. This version of the patch incorporates feedback from a review by Sean Silva. Thanks to all reviewers! Patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181204 91177308-0d34-0410-b5e6-96231b3b80d8
131 lines
2.9 KiB
LLVM
131 lines
2.9 KiB
LLVM
; Test 8-bit GPR stores.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test an i8 store, which should get converted into an i32 truncation.
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define void @f1(i8 *%dst, i8 %val) {
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; CHECK: f1:
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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store i8 %val, i8 *%dst
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ret void
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}
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; Test an i32 truncating store.
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define void @f2(i8 *%dst, i32 %val) {
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; CHECK: f2:
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%trunc = trunc i32 %val to i8
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store i8 %trunc, i8 *%dst
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ret void
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}
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; Test an i64 truncating store.
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define void @f3(i8 *%dst, i64 %val) {
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; CHECK: f3:
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%trunc = trunc i64 %val to i8
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store i8 %trunc, i8 *%dst
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ret void
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}
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; Check the high end of the STC range.
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define void @f4(i8 *%dst, i8 %val) {
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; CHECK: f4:
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; CHECK: stc %r3, 4095(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%dst, i64 4095
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store i8 %val, i8 *%ptr
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ret void
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}
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; Check the next byte up, which should use STCY instead of STC.
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define void @f5(i8 *%dst, i8 %val) {
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; CHECK: f5:
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; CHECK: stcy %r3, 4096(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%dst, i64 4096
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store i8 %val, i8 *%ptr
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ret void
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}
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; Check the high end of the STCY range.
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define void @f6(i8 *%dst, i8 %val) {
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; CHECK: f6:
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; CHECK: stcy %r3, 524287(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%dst, i64 524287
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store i8 %val, i8 *%ptr
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ret void
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}
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; Check the next byte up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f7(i8 *%dst, i8 %val) {
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; CHECK: f7:
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; CHECK: agfi %r2, 524288
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%dst, i64 524288
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store i8 %val, i8 *%ptr
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ret void
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}
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; Check the high end of the negative STCY range.
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define void @f8(i8 *%dst, i8 %val) {
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; CHECK: f8:
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; CHECK: stcy %r3, -1(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%dst, i64 -1
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store i8 %val, i8 *%ptr
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ret void
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}
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; Check the low end of the STCY range.
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define void @f9(i8 *%dst, i8 %val) {
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; CHECK: f9:
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; CHECK: stcy %r3, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%dst, i64 -524288
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store i8 %val, i8 *%ptr
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ret void
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}
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; Check the next byte down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f10(i8 *%dst, i8 %val) {
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; CHECK: f10:
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; CHECK: agfi %r2, -524289
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; CHECK: stc %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i8 *%dst, i64 -524289
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store i8 %val, i8 *%ptr
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ret void
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}
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; Check that STC allows an index.
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define void @f11(i64 %dst, i64 %index, i8 %val) {
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; CHECK: f11:
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; CHECK: stc %r4, 4095(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %dst, %index
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%add2 = add i64 %add1, 4095
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%ptr = inttoptr i64 %add2 to i8 *
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store i8 %val, i8 *%ptr
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ret void
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}
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; Check that STCY allows an index.
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define void @f12(i64 %dst, i64 %index, i8 %val) {
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; CHECK: f12:
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; CHECK: stcy %r4, 4096(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %dst, %index
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%add2 = add i64 %add1, 4096
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%ptr = inttoptr i64 %add2 to i8 *
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store i8 %val, i8 *%ptr
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ret void
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}
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