mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-13 07:29:38 +00:00
f28987b76e
This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
527 lines
20 KiB
TableGen
527 lines
20 KiB
TableGen
//===- ARMRegisterInfo.td - ARM Register defs --------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the ARM register file
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//===----------------------------------------------------------------------===//
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// Registers are identified with 4-bit ID numbers.
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class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
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field bits<4> Num;
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let Namespace = "ARM";
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let SubRegs = subregs;
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}
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class ARMFReg<bits<6> num, string n> : Register<n> {
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field bits<6> Num;
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let Namespace = "ARM";
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}
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// Subregister indices.
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let Namespace = "ARM" in {
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// Note: Code depends on these having consecutive numbers.
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def ssub_0 : SubRegIndex;
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def ssub_1 : SubRegIndex;
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def ssub_2 : SubRegIndex; // In a Q reg.
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def ssub_3 : SubRegIndex;
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def dsub_0 : SubRegIndex;
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def dsub_1 : SubRegIndex;
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def dsub_2 : SubRegIndex;
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def dsub_3 : SubRegIndex;
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def dsub_4 : SubRegIndex;
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def dsub_5 : SubRegIndex;
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def dsub_6 : SubRegIndex;
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def dsub_7 : SubRegIndex;
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def qsub_0 : SubRegIndex;
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def qsub_1 : SubRegIndex;
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def qsub_2 : SubRegIndex;
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def qsub_3 : SubRegIndex;
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def qqsub_0 : SubRegIndex;
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def qqsub_1 : SubRegIndex;
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}
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// Integer registers
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def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
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def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
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def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
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def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
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def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
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def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
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def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
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def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
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// These require 32-bit instructions.
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let CostPerUse = 1 in {
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def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
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def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
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def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
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def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
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def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
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def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>;
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def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
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def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>;
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}
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// Float registers
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def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">;
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def S2 : ARMFReg< 2, "s2">; def S3 : ARMFReg< 3, "s3">;
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def S4 : ARMFReg< 4, "s4">; def S5 : ARMFReg< 5, "s5">;
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def S6 : ARMFReg< 6, "s6">; def S7 : ARMFReg< 7, "s7">;
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def S8 : ARMFReg< 8, "s8">; def S9 : ARMFReg< 9, "s9">;
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def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">;
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def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
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def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;
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def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;
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def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">;
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def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
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def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">;
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def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
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def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
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def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
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def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
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// Aliases of the F* registers used to hold 64-bit fp values (doubles)
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let SubRegIndices = [ssub_0, ssub_1] in {
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def D0 : ARMReg< 0, "d0", [S0, S1]>, DwarfRegNum<[256]>;
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def D1 : ARMReg< 1, "d1", [S2, S3]>, DwarfRegNum<[257]>;
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def D2 : ARMReg< 2, "d2", [S4, S5]>, DwarfRegNum<[258]>;
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def D3 : ARMReg< 3, "d3", [S6, S7]>, DwarfRegNum<[259]>;
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def D4 : ARMReg< 4, "d4", [S8, S9]>, DwarfRegNum<[260]>;
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def D5 : ARMReg< 5, "d5", [S10, S11]>, DwarfRegNum<[261]>;
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def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>;
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def D7 : ARMReg< 7, "d7", [S14, S15]>, DwarfRegNum<[263]>;
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def D8 : ARMReg< 8, "d8", [S16, S17]>, DwarfRegNum<[264]>;
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def D9 : ARMReg< 9, "d9", [S18, S19]>, DwarfRegNum<[265]>;
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def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;
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def D11 : ARMReg<11, "d11", [S22, S23]>, DwarfRegNum<[267]>;
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def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>;
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def D13 : ARMReg<13, "d13", [S26, S27]>, DwarfRegNum<[269]>;
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def D14 : ARMReg<14, "d14", [S28, S29]>, DwarfRegNum<[270]>;
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def D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>;
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}
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// VFP3 defines 16 additional double registers
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def D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>;
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def D17 : ARMFReg<17, "d17">, DwarfRegNum<[273]>;
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def D18 : ARMFReg<18, "d18">, DwarfRegNum<[274]>;
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def D19 : ARMFReg<19, "d19">, DwarfRegNum<[275]>;
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def D20 : ARMFReg<20, "d20">, DwarfRegNum<[276]>;
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def D21 : ARMFReg<21, "d21">, DwarfRegNum<[277]>;
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def D22 : ARMFReg<22, "d22">, DwarfRegNum<[278]>;
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def D23 : ARMFReg<23, "d23">, DwarfRegNum<[279]>;
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def D24 : ARMFReg<24, "d24">, DwarfRegNum<[280]>;
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def D25 : ARMFReg<25, "d25">, DwarfRegNum<[281]>;
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def D26 : ARMFReg<26, "d26">, DwarfRegNum<[282]>;
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def D27 : ARMFReg<27, "d27">, DwarfRegNum<[283]>;
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def D28 : ARMFReg<28, "d28">, DwarfRegNum<[284]>;
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def D29 : ARMFReg<29, "d29">, DwarfRegNum<[285]>;
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def D30 : ARMFReg<30, "d30">, DwarfRegNum<[286]>;
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def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>;
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// Advanced SIMD (NEON) defines 16 quad-word aliases
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let SubRegIndices = [dsub_0, dsub_1],
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CompositeIndices = [(ssub_2 dsub_1, ssub_0),
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(ssub_3 dsub_1, ssub_1)] in {
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def Q0 : ARMReg< 0, "q0", [D0, D1]>;
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def Q1 : ARMReg< 1, "q1", [D2, D3]>;
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def Q2 : ARMReg< 2, "q2", [D4, D5]>;
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def Q3 : ARMReg< 3, "q3", [D6, D7]>;
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def Q4 : ARMReg< 4, "q4", [D8, D9]>;
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def Q5 : ARMReg< 5, "q5", [D10, D11]>;
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def Q6 : ARMReg< 6, "q6", [D12, D13]>;
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def Q7 : ARMReg< 7, "q7", [D14, D15]>;
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}
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let SubRegIndices = [dsub_0, dsub_1] in {
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def Q8 : ARMReg< 8, "q8", [D16, D17]>;
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def Q9 : ARMReg< 9, "q9", [D18, D19]>;
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def Q10 : ARMReg<10, "q10", [D20, D21]>;
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def Q11 : ARMReg<11, "q11", [D22, D23]>;
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def Q12 : ARMReg<12, "q12", [D24, D25]>;
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def Q13 : ARMReg<13, "q13", [D26, D27]>;
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def Q14 : ARMReg<14, "q14", [D28, D29]>;
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def Q15 : ARMReg<15, "q15", [D30, D31]>;
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}
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// Pseudo 256-bit registers to represent pairs of Q registers. These should
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// never be present in the emitted code.
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// These are used for NEON load / store instructions, e.g., vld4, vst3.
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// NOTE: It's possible to define more QQ registers since technically the
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// starting D register number doesn't have to be multiple of 4, e.g.,
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// D1, D2, D3, D4 would be a legal quad, but that would make the subregister
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// stuff very messy.
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let SubRegIndices = [qsub_0, qsub_1],
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CompositeIndices = [(dsub_2 qsub_1, dsub_0), (dsub_3 qsub_1, dsub_1)] in {
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def QQ0 : ARMReg<0, "qq0", [Q0, Q1]>;
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def QQ1 : ARMReg<1, "qq1", [Q2, Q3]>;
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def QQ2 : ARMReg<2, "qq2", [Q4, Q5]>;
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def QQ3 : ARMReg<3, "qq3", [Q6, Q7]>;
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def QQ4 : ARMReg<4, "qq4", [Q8, Q9]>;
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def QQ5 : ARMReg<5, "qq5", [Q10, Q11]>;
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def QQ6 : ARMReg<6, "qq6", [Q12, Q13]>;
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def QQ7 : ARMReg<7, "qq7", [Q14, Q15]>;
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}
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// Pseudo 512-bit registers to represent four consecutive Q registers.
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let SubRegIndices = [qqsub_0, qqsub_1],
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CompositeIndices = [(qsub_2 qqsub_1, qsub_0), (qsub_3 qqsub_1, qsub_1),
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(dsub_4 qqsub_1, dsub_0), (dsub_5 qqsub_1, dsub_1),
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(dsub_6 qqsub_1, dsub_2), (dsub_7 qqsub_1, dsub_3)] in {
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def QQQQ0 : ARMReg<0, "qqqq0", [QQ0, QQ1]>;
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def QQQQ1 : ARMReg<1, "qqqq1", [QQ2, QQ3]>;
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def QQQQ2 : ARMReg<2, "qqqq2", [QQ4, QQ5]>;
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def QQQQ3 : ARMReg<3, "qqqq3", [QQ6, QQ7]>;
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}
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// Current Program Status Register.
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def CPSR : ARMReg<0, "cpsr">;
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def FPSCR : ARMReg<1, "fpscr">;
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def ITSTATE : ARMReg<2, "itstate">;
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// Special Registers - only available in privileged mode.
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def FPSID : ARMReg<0, "fpsid">;
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def FPEXC : ARMReg<8, "fpexc">;
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// Register classes.
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//
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// pc == Program Counter
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// lr == Link Register
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// sp == Stack Pointer
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// r12 == ip (scratch)
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// r7 == Frame Pointer (thumb-style backtraces)
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// r9 == May be reserved as Thread Register
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// r11 == Frame Pointer (arm-style backtraces)
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// r10 == Stack Limit
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//
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def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
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SP, LR, PC)> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned ARM_GPR_AO[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7,
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ARM::R8, ARM::R9, ARM::R10, ARM::R11 };
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// For Thumb1 mode, we don't want to allocate hi regs at all, as we
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// don't know how to spill them. If we make our prologue/epilogue code
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// smarter at some point, we can go back to using the above allocation
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// orders for the Thumb1 instructions that know how to use hi regs.
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static const unsigned THUMB_GPR_AO[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
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GPRClass::iterator
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GPRClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_GPR_AO;
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return ARM_GPR_AO;
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}
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GPRClass::iterator
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GPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
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return ARM_GPR_AO + (sizeof(ARM_GPR_AO)/sizeof(unsigned));
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}
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}];
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}
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// restricted GPR register class. Many Thumb2 instructions allow the full
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// register range for operands, but have undefined behaviours when PC
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// or SP (R13 or R15) are used. The ARM ISA refers to these operands
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// via the BadReg() pseudo-code description.
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def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned ARM_rGPR_AO[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12,ARM::LR,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7,
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ARM::R8, ARM::R9, ARM::R10,
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ARM::R11 };
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// For Thumb1 mode, we don't want to allocate hi regs at all, as we
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// don't know how to spill them. If we make our prologue/epilogue code
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// smarter at some point, we can go back to using the above allocation
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// orders for the Thumb1 instructions that know how to use hi regs.
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static const unsigned THUMB_rGPR_AO[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
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rGPRClass::iterator
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rGPRClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_rGPR_AO;
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return ARM_rGPR_AO;
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}
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rGPRClass::iterator
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rGPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_rGPR_AO + (sizeof(THUMB_rGPR_AO)/sizeof(unsigned));
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return ARM_rGPR_AO + (sizeof(ARM_rGPR_AO)/sizeof(unsigned));
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}
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}];
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}
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// Thumb registers are R0-R7 normally. Some instructions can still use
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// the general GPR register class above (MOV, e.g.)
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def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>;
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// For tail calls, we can't use callee-saved registers, as they are restored
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// to the saved value before the tail call, which would clobber a call address.
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// Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of
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// this class and the preceding one(!) This is what we want.
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def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// R9 is available.
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static const unsigned ARM_GPR_R9_TC[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R9, ARM::R12 };
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// R9 is not available.
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static const unsigned ARM_GPR_NOR9_TC[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3,
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ARM::R12 };
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// For Thumb1 mode, we don't want to allocate hi regs at all, as we
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// don't know how to spill them. If we make our prologue/epilogue code
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// smarter at some point, we can go back to using the above allocation
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// orders for the Thumb1 instructions that know how to use hi regs.
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static const unsigned THUMB_GPR_AO_TC[] = {
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ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
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tcGPRClass::iterator
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tcGPRClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_GPR_AO_TC;
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return Subtarget.isTargetDarwin() ? ARM_GPR_R9_TC : ARM_GPR_NOR9_TC;
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}
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tcGPRClass::iterator
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tcGPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.isThumb1Only())
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return THUMB_GPR_AO_TC + (sizeof(THUMB_GPR_AO_TC)/sizeof(unsigned));
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return Subtarget.isTargetDarwin() ?
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ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned)) :
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ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned));
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}
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}];
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}
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// Scalar single precision floating point register class..
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def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)>;
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// Subset of SPR which can be used as a source of NEON scalars for 16-bit
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// operations
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def SPR_8 : RegisterClass<"ARM", [f32], 32, (trunc SPR, 16)>;
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// Scalar double precision floating point / generic 64-bit vector register
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// class.
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// ARM requires only word alignment for double. It's more performant if it
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// is double-word alignment though.
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def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
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(sequence "D%u", 0, 31)> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// VFP2 / VFPv3-D16
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static const unsigned ARM_DPR_VFP2[] = {
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ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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ARM::D4, ARM::D5, ARM::D6, ARM::D7,
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ARM::D8, ARM::D9, ARM::D10, ARM::D11,
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ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
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// VFP3: D8-D15 are callee saved and should be allocated last.
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// Save other low registers for use as DPR_VFP2 and DPR_8 classes.
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static const unsigned ARM_DPR_VFP3[] = {
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ARM::D16, ARM::D17, ARM::D18, ARM::D19,
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ARM::D20, ARM::D21, ARM::D22, ARM::D23,
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ARM::D24, ARM::D25, ARM::D26, ARM::D27,
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ARM::D28, ARM::D29, ARM::D30, ARM::D31,
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ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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ARM::D4, ARM::D5, ARM::D6, ARM::D7,
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ARM::D8, ARM::D9, ARM::D10, ARM::D11,
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ARM::D12, ARM::D13, ARM::D14, ARM::D15 };
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DPRClass::iterator
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DPRClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.hasVFP3() && !Subtarget.hasD16())
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return ARM_DPR_VFP3;
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return ARM_DPR_VFP2;
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}
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|
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DPRClass::iterator
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DPRClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
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if (Subtarget.hasVFP3() && !Subtarget.hasD16())
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return ARM_DPR_VFP3 + (sizeof(ARM_DPR_VFP3)/sizeof(unsigned));
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else
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return ARM_DPR_VFP2 + (sizeof(ARM_DPR_VFP2)/sizeof(unsigned));
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|
}
|
|
}];
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|
}
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|
|
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// Subset of DPR that are accessible with VFP2 (and so that also have
|
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// 32-bit SPR subregs).
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def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
|
|
(trunc DPR, 16)> {
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let SubRegClasses = [(SPR ssub_0, ssub_1)];
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}
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|
|
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// Subset of DPR which can be used as a source of NEON scalars for 16-bit
|
|
// operations
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def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
|
|
(trunc DPR, 8)> {
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let SubRegClasses = [(SPR_8 ssub_0, ssub_1)];
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}
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|
|
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// Generic 128-bit vector register class.
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def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
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|
(sequence "Q%u", 0, 15)> {
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|
let SubRegClasses = [(DPR dsub_0, dsub_1)];
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
// Q4-Q7 are callee saved and should be allocated last.
|
|
// Save other low registers for use as QPR_VFP2 and QPR_8 classes.
|
|
static const unsigned ARM_QPR[] = {
|
|
ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
|
|
ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15,
|
|
ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
|
|
ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7 };
|
|
|
|
QPRClass::iterator
|
|
QPRClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
return ARM_QPR;
|
|
}
|
|
|
|
QPRClass::iterator
|
|
QPRClass::allocation_order_end(const MachineFunction &MF) const {
|
|
return ARM_QPR + (sizeof(ARM_QPR)/sizeof(unsigned));
|
|
}
|
|
}];
|
|
}
|
|
|
|
// Subset of QPR that have 32-bit SPR subregs.
|
|
def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
|
128, (trunc QPR, 8)> {
|
|
let SubRegClasses = [(SPR ssub_0, ssub_1, ssub_2, ssub_3),
|
|
(DPR_VFP2 dsub_0, dsub_1)];
|
|
}
|
|
|
|
// Subset of QPR that have DPR_8 and SPR_8 subregs.
|
|
def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
|
128, (trunc QPR, 4)> {
|
|
let SubRegClasses = [(SPR_8 ssub_0, ssub_1, ssub_2, ssub_3),
|
|
(DPR_8 dsub_0, dsub_1)];
|
|
}
|
|
|
|
// Pseudo 256-bit vector register class to model pairs of Q registers
|
|
// (4 consecutive D registers).
|
|
def QQPR : RegisterClass<"ARM", [v4i64], 256, (sequence "QQ%u", 0, 7)> {
|
|
let SubRegClasses = [(DPR dsub_0, dsub_1, dsub_2, dsub_3),
|
|
(QPR qsub_0, qsub_1)];
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
// QQ2-QQ3 are callee saved and should be allocated last.
|
|
// Save other low registers for use as QPR_VFP2 and QPR_8 classes.
|
|
static const unsigned ARM_QQPR[] = {
|
|
ARM::QQ4, ARM::QQ5, ARM::QQ6, ARM::QQ7,
|
|
ARM::QQ0, ARM::QQ1, ARM::QQ2, ARM::QQ3 };
|
|
|
|
QQPRClass::iterator
|
|
QQPRClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
return ARM_QQPR;
|
|
}
|
|
|
|
QQPRClass::iterator
|
|
QQPRClass::allocation_order_end(const MachineFunction &MF) const {
|
|
return ARM_QQPR + (sizeof(ARM_QQPR)/sizeof(unsigned));
|
|
}
|
|
}];
|
|
}
|
|
|
|
// Subset of QQPR that have 32-bit SPR subregs.
|
|
def QQPR_VFP2 : RegisterClass<"ARM", [v4i64], 256, (trunc QQPR, 4)> {
|
|
let SubRegClasses = [(SPR ssub_0, ssub_1, ssub_2, ssub_3),
|
|
(DPR_VFP2 dsub_0, dsub_1, dsub_2, dsub_3),
|
|
(QPR_VFP2 qsub_0, qsub_1)];
|
|
|
|
}
|
|
|
|
// Pseudo 512-bit vector register class to model 4 consecutive Q registers
|
|
// (8 consecutive D registers).
|
|
def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (sequence "QQQQ%u", 0, 3)> {
|
|
let SubRegClasses = [(DPR dsub_0, dsub_1, dsub_2, dsub_3,
|
|
dsub_4, dsub_5, dsub_6, dsub_7),
|
|
(QPR qsub_0, qsub_1, qsub_2, qsub_3)];
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
// QQQQ1 is callee saved and should be allocated last.
|
|
// Save QQQQ0 for use as QPR_VFP2 and QPR_8 classes.
|
|
static const unsigned ARM_QQQQPR[] = {
|
|
ARM::QQQQ2, ARM::QQQQ3, ARM::QQQQ0, ARM::QQQQ1 };
|
|
|
|
QQQQPRClass::iterator
|
|
QQQQPRClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
return ARM_QQQQPR;
|
|
}
|
|
|
|
QQQQPRClass::iterator
|
|
QQQQPRClass::allocation_order_end(const MachineFunction &MF) const {
|
|
return ARM_QQQQPR + (sizeof(ARM_QQQQPR)/sizeof(unsigned));
|
|
}
|
|
}];
|
|
}
|
|
|
|
// Condition code registers.
|
|
def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
|
|
let isAllocatable = 0;
|
|
}
|