llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-20 12:31:40 +00:00

History

Tom Stellard b52bf6a3b3 R600/SI: Prefer SALU instructions for bit shift operations

All shift operations will be selected as SALU instructions and then
if necessary lowered to VALU instructions in the SIFixSGPRCopies pass.

This allows us to do more operations on the SALU which will improve
performance and is also required for implementing private memory
using indirect addressing, since the private memory pointers must stay
in the scalar registers.

This patch includes some fixes from Matt Arsenault.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8

2013-11-13 23:36:37 +00:00

Analysis

add more comments around the delinearization of arrays

2013-11-13 22:37:58 +00:00

AsmParser

[Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.

2013-11-08 23:28:16 +00:00

Bitcode

Extract a bc attr parsing helper that returns Attribute::None on error

2013-11-12 01:31:00 +00:00

CodeGen

DIEHash: Move header include to be first in the implementation file to flush out header inclusion ordering issues