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This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8
58 lines
1.6 KiB
LLVM
58 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=knl | FileCheck %s
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define i16 @mask16(i16 %x) {
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%m0 = bitcast i16 %x to <16 x i1>
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%m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
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%ret = bitcast <16 x i1> %m1 to i16
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ret i16 %ret
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; CHECK: mask16
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; CHECK: knotw
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; CHECK: ret
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}
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define i8 @mask8(i8 %x) {
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%m0 = bitcast i8 %x to <8 x i1>
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%m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
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%ret = bitcast <8 x i1> %m1 to i8
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ret i8 %ret
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; CHECK: mask8
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; CHECK: knotw
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; CHECK: ret
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}
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define i16 @mand16(i16 %x, i16 %y) {
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%ma = bitcast i16 %x to <16 x i1>
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%mb = bitcast i16 %y to <16 x i1>
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%mc = and <16 x i1> %ma, %mb
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%md = xor <16 x i1> %ma, %mb
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%me = or <16 x i1> %mc, %md
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%ret = bitcast <16 x i1> %me to i16
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; CHECK: kandw
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; CHECK: kxorw
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; CHECK: korw
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ret i16 %ret
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}
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; CHECK: unpckbw_test
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; CHECK: kunpckbw
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; CHECK:ret
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declare <16 x i1> @llvm.x86.kunpck.v16i1(<8 x i1>, <8 x i1>) nounwind readnone
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define i16 @unpckbw_test(i8 %x, i8 %y) {
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%m0 = bitcast i8 %x to <8 x i1>
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%m1 = bitcast i8 %y to <8 x i1>
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%k = tail call <16 x i1> @llvm.x86.kunpck.v16i1(<8 x i1> %m0, <8 x i1> %m1)
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%r = bitcast <16 x i1> %k to i16
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ret i16 %r
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}
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; CHECK: shuf_test1
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; CHECK: kshiftrw $8
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; CHECK:ret
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define i8 @shuf_test1(i16 %v) nounwind {
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%v1 = bitcast i16 %v to <16 x i1>
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%mask = shufflevector <16 x i1> %v1, <16 x i1> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%mask1 = bitcast <8 x i1> %mask to i8
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ret i8 %mask1
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}
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