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subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
77 lines
3.0 KiB
TableGen
77 lines
3.0 KiB
TableGen
//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the top level entry point for the Hexagon target.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Hexagon Subtarget features.
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//===----------------------------------------------------------------------===//
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// Hexagon Archtectures
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def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2",
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"Hexagon v2">;
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def ArchV3 : SubtargetFeature<"v3", "HexagonArchVersion", "V3",
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"Hexagon v3">;
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def ArchV4 : SubtargetFeature<"v4", "HexagonArchVersion", "V4",
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"Hexagon v4">;
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def ArchV5 : SubtargetFeature<"v5", "HexagonArchVersion", "V5",
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"Hexagon v5">;
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "HexagonSchedule.td"
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include "HexagonRegisterInfo.td"
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include "HexagonCallingConv.td"
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include "HexagonInstrInfo.td"
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include "HexagonIntrinsics.td"
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include "HexagonIntrinsicsDerived.td"
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def HexagonInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Hexagon processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, SchedMachineModel Model,
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list<SubtargetFeature> Features>
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: ProcessorModel<Name, Model, Features>;
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def : Proc<"hexagonv2", HexagonModel, [ArchV2]>;
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def : Proc<"hexagonv3", HexagonModel, [ArchV2, ArchV3]>;
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def : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>;
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def : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>;
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// Hexagon Uses the MC printer for assembler output, so make sure the TableGen
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// AsmWriter bits get associated with the correct class.
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def HexagonAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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bit isMCAsmWriter = 1;
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}
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def Hexagon : Target {
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// Pull in Instruction Info:
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let InstructionSet = HexagonInstrInfo;
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let AssemblyWriters = [HexagonAsmWriter];
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}
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